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Design Languages >> Verilog-AMS >> Connect Modules
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Message started by tushit on Nov 8^th, 2006, 10:46am

Title: Connect Modules
Post by tushit on Nov 8^th, 2006, 10:46am

I am trying to convert digital logic from a reg to an electric. For this I create a module as listed at the bottom.However, the electrical signal doesn't seem to follow the digital signal. I gave a CLK at the IN port and I notice that the electrical skips cycles of the clock once in a while.
Any idea why? I've tried adding $bound_step() in the analog code as well. Is it possible that it is following it, but the recordvars() doesn't capture it properly?
I'm using ncsim and spectre for the cosim.
Regards
Tushit

module connect_d2a (IN , OUT) ;

input IN ;
output OUT ;
logic IN ;
electrical OUT ;

parameter real V1 = 1.0 ;
parameter real V0 = 0.0 ;
parameter real VX = 2.5 ;
parameter real VZ = 5.0 ;
parameter real R0 = 1k;
parameter real R1 = 1k;
parameter real RX = 100;
parameter real RZ = 1M;

parameter real TRISE = 100p ;
parameter real TFALL = 100p ;

real v, r;

initial begin
case(IN)
1'b0 : begin v=V0; r = R0; end
1'b1 : begin v=V1; r = R1; end
1'bX : begin v=VX; r = RX; end
1'bZ : begin v=VZ; r = RZ; end
endcase
end

always @ IN begin
case (IN)
1'b0 : begin v=V0; r = R0; end
1'b1 : begin v=V1; r = R1; end
1'bX : begin v=VX; r = RX; end
1'bZ : begin v=VZ; r = RZ; end
endcase
end

analog begin
@ (posedge IN) ;
@ (negedge IN) ;
V(OUT) <+ transition(v, 0, TRISE, TFALL) + transition (r,0,TRISE,TFALL) * I(OUT);
end

endmodule