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Other CAD Tools >> Physical Verification, Extraction and Analysis >> vias extraction problems
https://designers-guide.org/forum/YaBB.pl?num=1163019774

Message started by jaqijak on Nov 8^th, 2006, 1:02pm

Title: vias extraction problems
Post by jaqijak on Nov 8^th, 2006, 1:02pm

Hi everybody,
I had recently a problem that may be a via or pin extraction problem:
I get an open circuit when extracting with Assura RCX in "C only" mode but a correct extraction when using "RC" option (although I have correct LVS -and visual- check on the layout).

I use Cadence 5.033, Assura version 5.1.41 with IBM 7WL V1.4.0.4DM design kit.

Did I something wrong, does somebody have any idea about this issue ?

Thanks a lot

Jaqijak

Title: Re: vias extraction problems
Post by Andrew Beckett on Jan 12^th, 2007, 6:22am

There's no such Assura version 5.1.41. I do recall seeing something similar to this a while back - you probably should try to use a recent version of Assura (3.1.6 is the latest).

Andrew.