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Simulators >> Circuit Simulators >> how to create macromodel in spectre
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Message started by avlsi on Nov 9^th, 2006, 11:09pm

Title: how to create macromodel in spectre
Post by avlsi on Nov 9^th, 2006, 11:09pm

Hi,

I want to design to a macromodel with components like capacitors ,resistors to emulate a device. So that i can use it like the VCVS as used for running opamp based simulations.

I would like to know the way to create the macromodel and then use it.

Thanks in advance.

Title: Re: how to create macromodel in spectre
Post by Ken Kundert on Nov 10^th, 2006, 7:19am

Use Verilog-A. It is available in every copy of Spectre.

-Ken

Title: Re: how to create macromodel in spectre
Post by avlsi on Nov 25^th, 2006, 11:30pm

hi,

I actually want to calculate a capacitance value based on the voltages given to its terminals. I have done this in SPICE.
I was using V(node1, node2) to get the voltage and calculate the capacitance values using an expression.
In spectre, I am unable to do the same thing. I am getting an error.

Is there a better way to use voltages in expressions.

Thanks in advance.

RE

Title: Re: how to create macromodel in spectre
Post by Ken Kundert on Nov 26^th, 2006, 4:19pm

The approach you are trying to take is very common, but is not correct. Doing it that way leads to a variety of problems. See http://www.designers-guide.org/Modeling/varactors.pdf for a description of what can go wrong it you use that approach and how to model a capacitor correctly.

-Ken

Title: Re: how to create macromodel in spectre
Post by Andrew Beckett on Dec 12^th, 2006, 2:17pm

I agree entirely with Ken in this specific case, but it is possible to formulate voltage dependent capacitors (preferrably using a charge-based approach) using the "bsource" component in spectre. This is internally implemented in Verilog-A, and allows voltage or current dependencies to be expressed using spectre syntax.

See spectre -h bsource for more details, or look in the documentation.

However, Verilog-A is a good thing to learn and have under your belt - it gives you far more flexibility than bsource does. Ken and Olaf's book The Designer's Guide to Verilog-AMS is a good place to start on this.

Regards,

Andrew.