The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> How to improve the SR of balanced OTA?
https://designers-guide.org/forum/YaBB.pl?num=1163389704

Message started by edwintsu on Nov 12^th, 2006, 7:48pm

Title: How to improve the SR of balanced OTA?
Post by edwintsu on Nov 12^th, 2006, 7:48pm

For high slew rate of balanced OTA, but i can't incease the tail current(for quiscent current limit) or decrease the load capacitor(for load step response).

What should i do? Have some good modified balanced OTA?

Title: Re: How to improve the SR of balanced OTA?
Post by loose-electron on Nov 13^th, 2006, 9:29am

Hm...

Last I checked....

I = C dv/dt

Can't touch I and can't touch C?

and you want to improve dV/dt?

If you stay with an OTA you are probably stuck. I or C need to change.

If you are willing to consider some non-linear systems that force current when the differential pair are not equal in input (not steady state for a high gain feedback system) there are some ways of throwing extra current in while slewing. An op-amp which goes to a voltage mode output throws extra current out all the time to maintain the desired voltage when slewing.

Also, consider a class AB type OTA structure. More power efficient.

Jerry

Title: Re: How to improve the SR of balanced OTA?
Post by ywguo on Nov 13^th, 2006, 10:09pm

Hi edwintsu,

Jerry is correct.

Would you please explain why you can't decrease the load cap? Will the phase margin decrease? Will the settle become slow?

Best regards,
Yawei

Title: Re: How to improve the SR of balanced OTA?
Post by edwintsu on Nov 15^th, 2006, 1:30am

Thank you , Jerry and Yawei!

If i decrease the load cap, the loop phase margin decrease.

The system load step response may produce malfunction, and lower the system efficieny.

Now i use alternative methods to reduce hysteresis voltage, need not improve the SR of balanced OTA.

Title: Re: How to improve the SR of balanced OTA?
Post by Pavel on Nov 15^th, 2006, 1:50am

Quote:

If i decrease the load cap, the loop phase margin decrease.

Use Miller capacitor for phase margin correction.

Title: Re: How to improve the SR of balanced OTA?
Post by loose-electron on Nov 18^th, 2006, 11:51am

Also, look at the additive phases of all stages of the amplifier.

And - Can also drop gain of stages down a bit to maintain the same output capacitor.

Will 60db of open loop gain get it done instead of 90 db ? (Or whatever numbers are relative to what you are doing.)

Jerry

Title: Re: How to improve the SR of balanced OTA?
Post by SATurn on Nov 24^th, 2006, 2:49pm

Hi,

If you have access to IEEE, you can also find some simple circuit techniques for increasing the SR without increasing the quescent current. For example you can see:

S. Mehrmanesh, and et al., "A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters," ISCAS'03.

SATurn

Title: Re: How to improve the SR of balanced OTA?
Post by RobG on Nov 30^th, 2006, 12:19pm

Jerry is correct, but it may be best to clarify. It is the Gm of the diff pair that you want to change. Changing the gain by lowering the output impedance won't give you the change you need.

To lower the gm of the diff pair you need to use more overdrive or use some resistive degeneration. Both eat up headroom. If this is an issue use a separate tail current source for each diff pair "side," and put the degenerating resistance between the sources. However, if you do this, be aware the noise from tail current sources is no longer a common mode signal.

Adaptive bias amplifiers also avoid slew rate limitations.

Title: Re: How to improve the SR of balanced OTA?
Post by avlsi on Mar 26^th, 2007, 3:51am

To improve the SR, you can try to use CLASS AB INPUT Stage by using cross coupling. This will help to improve the OTA SR performance.

There is an example in Gray and Meyer regarding this.