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Design Languages >> Verilog-AMS >> VCO model understanding
https://designers-guide.org/forum/YaBB.pl?num=1163592534

Message started by neoflash on Nov 15^th, 2006, 4:08am

Title: VCO model understanding
Post by neoflash on Nov 15^th, 2006, 4:08am

attached is the verilog a model from this web site. Can any one help me understand each line of this model?

I have a difficult time understanding below points:

1. what is inital_step?
2. why initial_step can be a trigger?
3. what kind of syntax is "V(out) <+ transition(n ? vh : vl, 0, tt);" ?

module osc1 (out);

output out; voltage out; // output signal
parameter real freq=1 from (0:inf); // output frequency
parameter real vl=-1; // high output voltage
parameter real vh=1; // low output voltage
parameter real tt=0.01/freq from (0:inf); // transition time of output
integer n;
real next;

analog begin
@(initial_step) begin
next = 0.5/freq + $abstime;
end
@(timer(next)) begin
n = !n;
next = next + 0.5/freq;
end
V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule

Title: Re: VCO model understanding
Post by neoflash on Nov 15^th, 2006, 4:57am

also, timer syntax seems should be:

timer(start, period);

Why only one variable is enough for timer here?

Title: Re: VCO model understanding
Post by stumcn on Nov 15^th, 2006, 8:33am

I'm fairly new to Verilog myself but I think(!) I can answer your questions.

Question 1 & 2.

The initial_step event will occur, naturally enough, at the first point of the simulation, ie 0s. Similarly, final_step will trigger an event at the last available point of the simulation.

Question 3.

The line V(out) <+ transition(n ? vh : vl, 0, tt); contains a conditional operator. Ignore the transition statement and look simply at V(out) <+ n ? vh : vl;. This means that if condition n is true (i.e, '1') then V(out) will equal vh; if not true, V(out) will equal vl. I'm assuming here that it's not the transition statement your querying but the operand within that statement.

Finally, about the syntax of timer(start, period).

This means the event will occur at 'start' and will repeat itself at multiples of 'period'. If 'period' is not specified, as in this case, then the event will only be triggered once at the time specified by 'start'.

I'm sure it could be explained more clearly than I've put it but I hope that helps.

Stu

Title: Re: VCO model understanding
Post by jbdavid on Dec 8^th, 2006, 11:38pm

for THIS model the timer(start, period) could have been used,
but since this was probably a simplification of a VCO model, where the period varies with the input,
recalculating NEXT each time is the only way to do it.. (without doing an integration, and a sine output)
in addition you can also, (as in a later question) generate a random number based on noise data, as a JITTER
value, and get a vco with jitter..

One could argue that it helps the student to learn by having minimal changes between the different versions of the models..
so you only have to focus on the deltas..
OTOH, maybe is best to start with the simplest models, and add ALL the components of the extra features as one goes along?
unfortunately the hardest thing it to try to do both!!

Title: Re: VCO model understanding
Post by Ken Kundert on Dec 9^th, 2006, 10:01am

The '<+' in the statement "V(out) <+ transition(n ? vh : vl, 0, tt);" is a contribution operator. It is like an assignment for signals on nodes, branches, and terminals. Assignment ('=') and contribution ('<+') are similar. However they differ in important ways.

Assignment is used to give values to variables. Assignment statements take the form
variable = expression;
Here the expression is evaluated and the resulting value replaces the current value held by the variable. It is illegal to use an assignment operator to give a value to a signal.

Contribution is used to give values to signals. Contribution takes the form
signal <+ expression
where a signal consists of an access function such as V or I applied to a node, branch, or terminal. It is illegal to use a contribution operator to give a value to a variable. Contribution differs from assignment in two important ways. First all contributions to a signal from within a module are summed. So
V(out) <+ 2;
V(out) <+ 3;
results in V(out) being 5. This is useful because it allows the code that describes different effects to be modularized. So for example, to model a resistive sinusoidal source (a port) one could use
V(out) <+ 2*offset; // model the dc level
V(out) <+ 2*ampl*sin(`M_TWO_PI*freq*$abstime); // model the sinusoidal output voltage
V(out) <+ res*I(out); // model output resistance
V(out) <+ 8*`P_K*$temperature*res; // model noise

The second difference is that contributions form an equation that is solved. So for example, with
k = k + j;
the value of k is incremented by j, whereas with
V(out) <+ V(out) + V(in);
the resulting equation is solved to get "0 = V(in)" (here I use = to imply mathematical equality rather than assignment). So this statement in effect forces V(in) to 0. Such a statement can be used to build an ideal opamp.

The transition function converts piecewise constant value streams to continuous piecewise linear waveforms that are suitable for signals that might drive capacitors or inductors. It does this by adding a finite transition time. As a convenience it also allows you to specify a delay to the transformation.

-Ken