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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> A question about PLL behavior simulation. https://designers-guide.org/forum/YaBB.pl?num=1163644737 Message started by Terry on Nov 15th, 2006, 6:38pm |
Title: A question about PLL behavior simulation. Post by Terry on Nov 15th, 2006, 6:38pm Hi everyone, when I use behavior models for jitter simulation such as: Phase-frequency detectors (with jitter) Voltage controlled oscillators (with jitter) ....... getting from http://www.designers-guide.org/VerilogAMS/ I found that "vco" (with white accumulating jitter) model conflicted with "pfd_cp2"( with white Gaussian synchronous jitter) model when I add "vco" model even did not connet the "vco"'s "in" pin to "pfd_cp2"'s "out" pin. The "pfd_cp2"'s "out" pin was fixed to votage zero , and it has no port current. However, when I removed the alone "vco" model , I could see the voltage of filter that connectted to the "out" pin of "pfd_cp2" hehaved nomally, also I could see the current form the pin. Why the "vco" and "pdf_cp2" model conflicted? My simulation tools were spectre, verilog_A. The verilog_A code and netlist is listed behind. --------------------------do not add vco2---------------------------------------- simulator lang=spectre global 0 include "/tools/cadence/IC5141/tools.lnx86/dfII/samples/artist/ahdlLib/quantity.spectre" // Library name: pll // Cell name: pll_jitter_sim // View name: schematic I12 (net09 net08) divider2 V0 (net08 0) vsource type=pulse val0=2.5 val1=0 period=200.0n rise=1n \ fall=1n width=100.0n V1 (net022 0) vsource type=pulse val0=2.5 val1=0 period=30.52u rise=1n \ fall=1n width=15u C6 (net8 0) capacitor c=84p C0 (net010 0) capacitor c=547p R0 (net8 net010) resistor r=200K I11 (net8 net022 net09) pfd_cp2 tran tran stop=1m write="spectre.ic" writefinal="spectre.fc" \ annotate=status maxiters=5 ---------------------------------add vco2-------------------------------- simulator lang=spectre global 0 include "/tools/cadence/IC5141/tools.lnx86/dfII/samples/artist/ahdlLib/quantity.spectre" // Library name: pll // Cell name: pll_jitter_sim // View name: schematic I18 (net012 net011) vco2 I12 (net09 net08) divider2 V0 (net08 0) vsource type=pulse val0=2.5 val1=0 period=200.0n rise=1n \ fall=1n width=100.0n V1 (net022 0) vsource type=pulse val0=2.5 val1=0 period=30.52u rise=1n \ fall=1n width=15u C6 (net8 0) capacitor c=84p C0 (net010 0) capacitor c=547p R0 (net8 net010) resistor r=200K I11 (net8 net022 net09) pfd_cp2 simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \ sensfile="../psf/sens.output" checklimitdest=psf tran tran stop=1m write="spectre.ic" writefinal="spectre.fc" \ annotate=status maxiters=5 -------------------------------------------------------------------------- // vco // Voltage controlled oscillator with white accumulating jitter // module vco2 (out, in); input in; voltage in; // input terminal output out; voltage out; // output terminal parameter real vmin=-0.5; // input voltage that corresponds to minimum output frequency parameter real vmax=vmin+2.5 from (vmin:inf); // input voltage that corresponds to maximum output frequency parameter real fmin=-20M from (-inf:inf); // minimum output frequency parameter real fmax=100M from (fmin:inf); // maximum output frequency //parameter real fmax=2*fmin from (fmin:inf); // maximum output frequency parameter real vl=0; // high output voltage parameter real vh=2.5; // low output voltage parameter real tt=0.01/fmax from (0:inf); // output transition time parameter real ttol=1u/fmax from (0:1/fmax); // time tolerance parameter real jitter=1n from [0:0.25/fmax); // period jitter (produces white accumulating jitter) real freq, phase, dT; integer n, seed; analog begin @(initial_step) seed = -561; // compute the freq from the input voltage freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin; // bound the frequency (this is optional) if (freq > fmax) freq = fmax; if (freq < fmin) freq = fmin; // add the phase noise freq = freq/(1 + dT*freq); // bound the time step to assure no cycles are skipped $bound_step(0.05/freq); // phase is the integral of the freq modulo 2p phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5); // update jitter twice per period // `M_SQRT2=sqrt(K), K=2 jitter updates/period @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol)) begin dT = `M_SQRT2*jitter*$rdist_normal(seed,0, 1); n = (phase >= -`M_PI/2) && (phase < `M_PI/2); end // generate the output V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule ----------------------------------------------------------------------------- |
Title: Re: A question about PLL behavior simulation. Post by Terry on Nov 15th, 2006, 6:41pm // // This model exhibits white synchronous jitter // module divider2 (out, in); output out; voltage out; // output input in; voltage in; // input (edge triggered) parameter real vh=+2.5; // output voltage in high state parameter real vl=0; // output voltage in low state parameter real vth=(vh+vl)/2; // threshold voltage at input parameter integer ratio=800 from [2:inf); // divide ratio parameter integer dir=1 from [-1:1] exclude 0; // dir=1 for positive edge trigger // dir=-1 for negative edge trigger parameter real tt=1n from (0:inf); // transition time of output signal parameter real td=100n from (0:inf); // average delay from input to output parameter real jitter=10n from [0:td/5); // edge-to-edge jitter parameter real ttol=1p from (0:td/5); // time tolerance, recommend ttol << jitter integer count, n, seed; real dt; analog begin @(initial_step) seed = -311; @(cross(V(in) - vth, dir, ttol)) begin count = count + 1; // count input transitions if (count >= ratio) count = 0; n = (2*count >= ratio); dt = jitter*$rdist_normal(seed,0,1); // add jitter end V(out) <+ transition(n ? vh : vl, td+dt, tt); end endmodule --------------------------------------------------------------------------- // // This model exhibits white gaussian synchronous jitter // module pfd_cp2 (out1, ref, vco); output out1; electrical out1; // current output input ref; voltage ref; // positive input (edge triggered) input vco; voltage vco; // inverting input (edge triggered) parameter real iout=2u; // maximum output current parameter real vh=2.5; // output voltage in high state parameter real vl=0; // output voltage in low state parameter real vth=(vh+vl)/2; // threshold voltage at input parameter integer dir=1 from [-1:1] exclude 0; // dir=1 for positive edge trigger // dir=-1 for negative edge trigger parameter real tt=1n from (0:inf); // transition time of output signal parameter real td=5n from (0:inf); // average delay from input to output parameter real jitter=0.8n from [0:td/5); // white edge-to-edge jitter parameter real ttol=1p from (0:td/5); // time tolerance, recommend ttol << jitter integer state, seed; real dt; analog begin @(initial_step) seed = 716; @(cross(V(ref)-vth, dir, ttol)) begin if (state > -1) state = state - 1; dt = jitter*$rdist_normal(seed,0,1); end @(cross(V(vco)-vth, dir, ttol)) begin if (state < 1) state = state + 1; dt = jitter*$rdist_normal(seed,0,1); end I(out1) <+ transition(iout*state, td + dt, tt); end endmodule |
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