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Design Languages >> Verilog-AMS >> how we probe local variables in verilog-A sim
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Message started by neoflash on Nov 15^th, 2006, 9:35pm

Title: how we probe local variables in verilog-A sim
Post by neoflash on Nov 15^th, 2006, 9:35pm

I am using hspice simulator. How to observe those internal non-electrical signals?

Title: Re: how we probe local variables in verilog-A sim
Post by Geoffrey_Coram on Nov 16^th, 2006, 11:27am

Per the new Verilog-AMS LRM, you can define output variables with attributes,

If you have a variable called "iavl" that is used to store the avalanche current, declare it at top level (module scope, not in a named block) with

(* desc="avalanche current" *) real iavl;

(and, obviously, remove the declaration you had before). I believe HSpice supports this new feature. I forget the exact syntax, though, for requesting that HSpice save it to the .tr0 file; I think it's similar to what you do for saving "gm" from a transistor.

Title: Re: how we probe local variables in verilog-A sim
Post by neoflash on Nov 18^th, 2006, 6:15am

oh.

Maybe I will check with hspice manual. It is quite ridiculous that my CAD engineer does not install the manual with new version simulator, thus I have to live without that for quite long time, until that guy have time to handle my request...