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Design Languages >> Verilog-AMS >> Simultaion under ADvance MS
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Message started by skagoods on Nov 17^th, 2006, 10:20am

Title: Simultaion under ADvance MS
Post by skagoods on Nov 17^th, 2006, 10:20am

Hello,

I'm a beginner in Mixed simulation, and I have to use ADvance MS from Mentor Graphics. What I am doing is modeling an audio DAC in verilog AMS with as input an external file (data_in.dat). Since the input is digital, I use a Verilog module to import it and after I have to feed the DAC with these input from the external file.
What I want to know is what is the best methodology for such a thing: use the verilog file as the top module and then instantiate the Verilog-AMS module directly from the Verilog module (I already tried, but there is a problem since the output of the DAC in analog and I instantiate it from a digital context, I am told that there is an illegal connection)? Or use a Eldo file as top module, and then instantiate both modules (Verilog and Verilog AMS) from there (I also tried but there's also a problem in the connection between std_logic and electrical)?

I'm really beginning is that field and I would really appreciate just if you can tell me what methodology would better than others please.

Cheers everybody,

Florian