The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> [q] in simulating verilog-a in hspice
https://designers-guide.org/forum/YaBB.pl?num=1163817214

Message started by kidhyun on Nov 17th, 2006, 6:33pm

Title: [q] in simulating verilog-a in hspice
Post by kidhyun on Nov 17th, 2006, 6:33pm

Dear,

  I wrote the following in the analog block in the verilog-a module.
 
analog begin

     @ ( initial_step ) begin
      sigout_file = $fopen( "out.m" );
      $fstrobe(sigout_file,"%% %s sampled at %g Hz.", "Sine Wave", 1/tsample);
      $fstrobe(sigout_file,"%% Generated by Spectre from instance `%M'");
                $fstrobe(sigout_file,"outv=[ ");
      next_sample_time = tsample;
     end
   

     @ ( timer( next_sample_time )) begin
      if (log_time == 1 ) begin
                    $fwrite(sigout_file, "%-.10g\t%-.10g", $abstime, V(sigin));
      end else begin
                    $fwrite(sigout_file, "%-.10g ", V(sigin));
                end
     //end
               if ($abstime >= next_sample_time)
                     next_sample_time = next_sample_time + tsample;
     end

     @ ( final_step ) begin
               $fstrobe(sigout_file, "]");
               $fclose(sigout_file);
     end
end

But the fstrobe commands in the initial block are executed twice.
(In the output file, there are 2 duplicates of sentences at the head.)
I don't get what's wrong with this initial keyword.

Thank You


 

Title: Re: [q] in simulating verilog-a in hspice
Post by Ken Kundert on Nov 17th, 2006, 10:39pm

It might be because the initial_step is firing both in the IC phase and the transient phase of the transient analysis. It should not do that. You might be able to work around it either by adding "uic" to the transient analysis statement, or by adding an "if (!analysis("ic"))" to your module definition.

-Ken

Title: Re: [q] in simulating verilog-a in hspice
Post by neoflash on Nov 18th, 2006, 6:11am

how we probe those local variables inside verilog-a model in spice simulation?

This will make debug possible.

Title: Re: [q] in simulating verilog-a in hspice
Post by Geoffrey_Coram on Nov 21st, 2006, 5:58am


neoflash wrote on Nov 18th, 2006, 6:11am:
how we probe those local variables inside verilog-a model in spice simulation?


Didn't you ask the same question in this thread:
http://www.designers-guide.org/Forum/YaBB.pl?num=1163655345
?

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.