The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Difference between voltage and electrical https://designers-guide.org/forum/YaBB.pl?num=1163862804 Message started by neoflash on Nov 18th, 2006, 7:13am

Title: Difference between voltage and electrical Post by neoflash on Nov 18th, 2006, 7:13am Some coder directly declare signal as voltage instead of electrical, what is the difference? Can we also declare current type signal?

Title: Re: Difference between voltage and electrical Post by Geoffrey_Coram on Nov 20th, 2006, 4:33am neoflash wrote on Nov 18th, 2006, 7:13am: Some coder directly declare signal as voltage instead of electrical, what is the difference? Can we also declare current type signal? Yes.  These are known as "signal flow disciplines" and I think they're used when you don't care to enforce KCL and KVL, you are just propagating a value.  Some simulators may be able to simulate this more efficiently.  I haven't used this capability myself.

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