The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> LDO under rapid load current change
https://designers-guide.org/forum/YaBB.pl?num=1164188477

Message started by uncle_ezra on Nov 22^nd, 2006, 1:41am

Title: LDO under rapid load current change
Post by uncle_ezra on Nov 22^nd, 2006, 1:41am

Suppose you have a LDO and I simulate the response of Vout under a rapid rise and fall time of 1ps in load current. In frequency domain the rise time is just the Laplace transform of a step function which is 1/s. So if the frequency response of the LDO has peaking after unity gain frequency this test will trigger oscillation even for an adequate phase margin. Is my thinking right? At least I am observing this in simulation, so I am trying to explain the reasoning behind it.

Thanks

Title: Re: LDO under rapid load current change
Post by vivkr on Nov 22^nd, 2006, 2:46am

uncle_ezra wrote on Nov 22^nd, 2006, 1:41am:

S. So if the frequency response of the LDO has peaking after unity gain frequency this test will trigger oscillation even for an adequate phase margin.

Thanks

Hi,

If your frequency response has appreciable peaking after unity gain frequency, then why are you looking only at phase margin? Your system has too little gain margin. Since it is an LDO, I am guessing you have problems with the complex pole pair that you get due to the load cap. If it oscillates, it cannot be a stable system.

Regards
Vivek

Title: Re: LDO under rapid load current change
Post by loose-electron on Nov 27^th, 2006, 12:26pm

Two questions:

What is the ESR (effective series resistance) of your decoupling capacitance? (This plays heavly into the phase margin of your system.)

What is the voltage, and resulting gain, of your output transisotr? (In an LDO this varies by 30db or so, depending on operating point.)

Take a close look at these two items, they affect stability in a big way.

Jerry

Title: Re: LDO under rapid load current change
Post by uncle_ezra on Nov 27^th, 2006, 8:57pm

Hi,

Thanks for all your reply. From measurement and simulation my LDO is unstable for high ESR > 8 Ohms. However if I place two low Q capacitors (10uF and 1uF) in parallel the LDO is stable. Does placing two parallel high ESR capacitors decrease the overall ESR? How does this work? If I place a third capacitor (1uF) in parallel the LDO is unstable. Any reasonings?

Thanks

Title: Re: LDO under rapid load current change
Post by loose-electron on Nov 28^th, 2006, 9:16am

Do the equivalent networks of what you are doing (Laplace transforms, S Plane will work) and you will see that you are shifting the phase margin of the system all over the place by doing this.

Jerry