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Design Languages >> Verilog-AMS >> Synthesis Problem With Capture Program
https://designers-guide.org/forum/YaBB.pl?num=1164333355

Message started by EEStyx on Nov 23^rd, 2006, 5:55pm

Title: Synthesis Problem With Capture Program
Post by EEStyx on Nov 23^rd, 2006, 5:55pm

I am trying to make a program that captures the codes from an infrared decoder. I designed this program to measure the time between the bits (unipolar, return to zero) and determine what the last bit was.

The problem is that every time I compile the program using Quartus II (version 5) the compiler sythesizes away all of the registers to GND. I think it might have something to do with the time required for the logic to do anything, but I'm not sure. Does anyone have any ideas? Any help on the issue would be GREATLY appreciated.

Thanks in advance.

The Code:
(Note: There is an additional always block after this, but its only used to display the stored codes to a 7-seg display)
(Note: There have been comments added, so pay attention to the comment lines)

module NewCapture (Clk100khz, irIn, WordOut, Cycle, DipIn, CaptureEn, Reset);
input Clk100khz, irIn, Cycle, Reset;
input [3:0] DipIn;
output [7:0] WordOut;
output CaptureEn;
reg [7:0] WordOut;
reg [11:0] OffTime; // Used to count the space between logic one's
reg [11:0] OnTime; // Used to count the on-time: used for verification of the 'start' code
reg [55:0] CurrentWord; // Used to store the incomming instruction set

// Each intsruction set will be stored to a different register for evaluation
// A total of 10 instructions may be stored
reg [55:0] Instrctn1, Instrctn2, Instrctn3, Instrctn4, Instrctn5;
reg [55:0] Instrctn6, Instrctn7, Instrctn8, Instrctn9, Instrctn10;

// Used to evaluate the previous status of ir compared to the current value
// Will be used to find the rising edge of irIn.
reg PrevIrVal;
reg CaptureEn; // If it is ok to enable code-storing
reg [1:0] PrevBit;
reg [3:0] CodeNum; // Used to determine which instruction set is being stored
reg StartCode; // If the start code FF has been seen, set StartCode

// For displaying the code to the 7-seg displays
reg [55:0] DispTemp;
integer n;

always @ (posedge Clk100khz)
begin

if (!CaptureEn)
begin

if (irIn)
begin
OnTime = OnTime + 1;
// if the irIn is on for more than 8-bits, non-return to zero
// then the start code has been recieved
if (OnTime >> 12'h320) // Time value for start code of '11111111' of '111111110000'
begin
OnTime = 0;
StartCode = 1;
end // end if (OnTime >> value)
end // end if (irIn)

else // else, then irIn is false
begin
OnTime = 0;
if (StartCode) CaptureEn = 1;
else;
end
end // end if (!CaptureEn)

else if (CaptureEn)
begin
StartCode = 0;

// find the rising edge of irIn to compute and store ir-code
if (irIn && !PrevIrVal)
begin
OffTime = 0;
PrevIrVal = 1;
CurrentWord = CurrentWord << 1;

// if a '11x' was recieved
// Tmin = 40 < time < Tmax = 80
if ((OffTime >> 12'h028) && (OffTime << 12'h050))
begin
CurrentWord[0] = 1;
PrevBit = 2'b11; // bit was 1
end

// if a '10x' was recieved
// Tmin = 50h, Tmax = BAh
else if ((OffTime >> 12'h050) && (OffTime << 12'h0BA))
begin
CurrentWord = CurrentWord << 1;
CurrentWord[1:0] = 2'b01;
PrevBit = 2'b10; // bit was 0
end

// if a '100x' was recieved
// Tmin = EFh Tmax = 2B3
else if ((OffTime >> 12'h0EF) && (OffTime << 12'h10A))
begin
CurrentWord = CurrentWord >> 1;
//CurrentWord[0] = 1;
PrevBit = 2'b01; // error or end of instruction
end

// of a '1000x' was recieved
else if ((OffTime >> 12'h10A) && (OffTime << 12'h175))
begin
CurrentWord = CurrentWord >> 1;
PrevBit = 2'b01;
end

// if a 'x00001' was recived
else if (OffTime >> 12'h175)
begin
CurrentWord[0] = 1;
PrevBit = 2'b11;
end

else;
end // end if (irIn && !PrevValue)

else if (!irIn)
begin
PrevIrVal = 0;
OffTime = OffTime + 1;

// if between instruction bits:
// if 8 zeros in a row:
if (OffTime == 12'h2C4)
begin

if (CodeNum == 4'b0000)
begin
Instrctn1 = 0;
Instrctn1 = CurrentWord;
end
else if (CodeNum == 4'b0001)
begin
Instrctn2 = 0;
Instrctn2 = CurrentWord;
end
else if (CodeNum == 4'b0010)
begin
Instrctn3 = 0;
Instrctn3 = CurrentWord;
end
else if (CodeNum == 4'b0011)
begin
Instrctn4 = 0;
Instrctn4 = CurrentWord;
end
else if (CodeNum == 4'b0100)
begin
Instrctn5 = 0;
Instrctn5 = CurrentWord;
end
else if (CodeNum == 4'b0101)
begin
Instrctn6 = 0;
Instrctn6 = CurrentWord;
end
else if (CodeNum == 4'b0110)
begin
Instrctn7 = 0;
Instrctn7 = CurrentWord;
end
else if (CodeNum == 4'b0111)
begin
Instrctn8 = 0;
Instrctn8 = CurrentWord;
end
else if (CodeNum == 4'b1000)
begin
Instrctn9 = 0;
Instrctn9 = CurrentWord;
end
else if (CodeNum == 4'b1001)
begin
Instrctn10 = 0;
Instrctn10 = CurrentWord;
end
else;

CodeNum = CodeNum + 1;
CurrentWord = 0;
end // end if ((OffTime >> 12'h2C4) && (OffTime << 12'h881))

// if more than 20 bits have passed, the button is done
else if (OffTime >> 12'h881)
begin
CodeNum = 4'b0000;
CaptureEn = 0;
OffTime = 0;
end
else;
end // end else if (!irIn)
end // end else if (CaptureEn)
else;
end // end always
endmodule

Title: Re: Synthesis Problem With Capture Program
Post by jbdavid on Dec 8^th, 2006, 11:22pm

Many have read this, but few reply.. mainly because most of the eyeballs watching this forum are driven by analog guys...

Title: Re: Synthesis Problem With Capture Program
Post by EEStyx on Dec 11^th, 2006, 9:54am

To anyone who was interested in the solution, I was finally able to determine why it wasn't working correctly.

The program that was posted uses all blocking statements ( = ). For some reason, unknown to me, the synthesis program interrpreted these incorrectly and compiled all storage registers to grounds. When all the statements are changed to non-blocking ( <= ) everything works perfectly.

Like I say, Im not sure why it works like that, but it does.