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Design Languages >> VHDL-AMS >> Question on Jitter Tolerance Pattern Gen Code
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Message started by neoflash on Nov 24^th, 2006, 9:10am

Title: Question on Jitter Tolerance Pattern Gen Code
Post by neoflash on Nov 24^th, 2006, 9:10am

I'm reading code from Paul Muller, which is available from this web site.
However, the part on sj_src is pretty strange. Why in quoted line need to multiply freq and sj_freq twice? Is it a typo?

architecture bhv of sj_src is
constant sj_tau : time := 10ps;
quantity vsj_out across isj_out through sj_out;
quantity vsj_int : voltage;
begin
-- All quantities considered in a 50 Ohm environment
-- Voltage source is 2 * effective voltage
-- sj_amp is considered a PP voltage
-- output signal is centered around Vdd/2=0.0V

Quote:

vsj_int == 2.0 * (0.0 + 0.9 * 0.5 * sj_amp * sin(MATH_2_PI*sj_freq*freq*NOW));

vsj_out == vsj_int + isj_out * 50.0;
end bhv;

Title: Re: Question on Jitter Tolerance Pattern Gen Code
Post by Paul on Dec 17^th, 2006, 3:02pm

Hi,

Sorry for the late reply, I was rather busy these last weeks. If I understand your question correctly, you would like to know where the sj_freq*freq product comes from. It is simply due to the fact that in most standards, SJ frequency is represented as a metric normalized to the signal frequency (=bit rate). In order to get the effective SJ frequency in Hz (or GHz), you have to multiply the normalized SJ frequency by the signal frequency.

Does this answer your question?

Best,
Paul