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Design Languages >> Verilog-AMS >> Help Required for Veriloga Code of NAND gate
https://designers-guide.org/forum/YaBB.pl?num=1164396930

Message started by junaidgill on Nov 24^th, 2006, 11:35am

Title: Help Required for Veriloga Code of NAND gate
Post by junaidgill on Nov 24^th, 2006, 11:35am

hello,
i am new to verilog-a and i am trying to write code for NAND gate. can anyone please help me to complete the behvior:

module NAND(in1, in2, out)

inout in1, in2;
output out;
electrical in1, in2, out;

parameter real vlogic_high = 3.5;

//behvior of NAND GATE (i need help in this part)

endmodule

i know that i should make use of @(cross(V(in1) - thresh, +1)) but i don't know the correct way.

Title: Re: Help Required for Veriloga Code of NAND gate
Post by Ken Kundert on Nov 24^th, 2006, 11:28pm

I just added some examples to the Verilog-AMS page. Take a look at http://www.designers-guide.org/VerilogAMS/functional-blocks/gates/gates.va.

-Ken

Title: Re: Help Required for Veriloga Code of NAND gate
Post by junaidgill on Nov 25^th, 2006, 2:01am

thankyou very much Ken... those are really very helpful examples.....

Title: Re: Help Required for Veriloga Code of NAND gate
Post by Q8i on Nov 28^th, 2006, 6:28pm

Could you please add the same thing for Verilog AMS
i mean the and , or ,xor code for Verilog AMS If you don't mind

Title: Re: Help Required for Veriloga Code of NAND gate
Post by Ken Kundert on Nov 29^th, 2006, 12:13am

You can use the gates built-in to verilog when using Verilog-AMS.

But here is a behavioral model for a nand gate in verilog.

Code:

module mynand(in1, in2, out);
input in1, in2;
output out;
assign out = ~(in1 & in2);
endmodule

-Ken