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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> How to replace "wait" in synthesis ?!? https://designers-guide.org/forum/YaBB.pl?num=1164570850 Message started by AdamPod on Nov 26th, 2006, 11:54am |
Title: How to replace "wait" in synthesis ?!? Post by AdamPod on Nov 26th, 2006, 11:54am Hi, I need to replace "wait" statement in order to perform synthesis of my behavioral model... Is there any known way to do this ?!? I found on the www.eecs.berkeley.edu/~chinnery/synthesizableVerilog.html website some solution, by it does not fulfil all my requirements. Below is a peace of my code I need to synthesize: always@(state) begin case (state) read: begin XEN_EEPROM_Read <= 1'b1; eeprom_reading <= 1; ER <= read_test_count; wait (eeprom_reading == 0); if (ED_int == EV_test) failure <= 0; else failure <= 1; parity <= ~parity; read_test_count <= read_test_count + 1; state <= idle; end ....... eeprom_reading signal is set to zero when appropriate counter reach given value - the whole process is put in separate "always" block. In the rest of the cases there is no more of "wait" statements. I will be glad if anyone knew how rewrite this code properly and could gice my some hint. |
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