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Design >> Mixed-Signal Design >> problem in Charge pump design
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Message started by Esther on Nov 30^th, 2006, 12:40am

Title: problem in Charge pump design
Post by Esther on Nov 30^th, 2006, 12:40am

Hi all,

I am designing a charge pump for pll now. I meet several problem about it. Could any body give me some advices?

1. bootstrapping of the CP. I use a Opamp with unity gain connection. But the speed of Opamp is slow for the circuit. see, if fref is 100MHz, 10ns period, slew rate 1.0V/50ns Opamp can not pull the bootstrapping point to Vctrl immediately. But most of papers just use Opamp, seldom talk about this detail. Anybody can help me?

2. about UP/DOWN switches. Is it nenessary to use tranmission gate rather than just one NMOS or PMOS transistor? Any concern about this? Also same questions for switches in bootstrapping path.

3. I can not remove the current glitch when switch turns on or off. But I think that will not cause big problem since low pass filter can filter these high frequency glitches. Am I correct on this point?

4. How to simulate stabitility and noise of charge pump? Is that nenessary? I only do DC and transient sim right now.

Thank you in advance.
Esther

Title: Re: problem in Charge pump design
Post by loose-electron on Nov 30^th, 2006, 8:20am

Esther:

I presume that this is a standard charge pump with a pair of complementary switches and current sources above and below. The op-amp is getting used to maintain the voltage that the switch flips over to when you are not pumping up or down.

That op-amp needs to have bandwidth necessary to meet the loop bandwidth. Essentially enough BW to track what is happening at the loop filter voltage.

Switches - these don't need to be both PMOS/NMOS if the resistance of the switches is OK over the full operating range of the filter voltage.

Switches - Doing a charge compensated switch (research switched capacitor circuit design for more info here) will help minimize the effects of charge injection.

Stability of the charge pump alone? - There is no feedback path here so, not needed.

Noise of the charge pump? - A lot of the effects here are going to get killed off through the loop filter and the feedback system.

Hope that helps,
Jerry

Title: Re: problem in Charge pump design
Post by Esther on Nov 30^th, 2006, 5:26pm

Hi,Jerry

Very nice to get your help. Thank you. Yes, I am talking about a standard charge pump as you mentioned.

I have 2 more quesitons following your explain.

1. about bandwidth of Opamp for bootstrapping charge pump. I think the bandwidth just bigger than pll bandwidth is not enough. We hope the Opamp can pull the switch node equal to Vctrl during the switch is off. but the time period when switch is off may be very short, for example, refclk and fbclk have big phase difference. But the Opamp should response and pull the switch node to Vctrl even in this short period, which is what we want. From this point of view, the Opamp should be very fast one, I even don't know how to define the required speed for the Opamp since the bootstrapping period can be infinite small....

2. For the compensated switch to reduce injection charge, would you give me more infomation. I am very interested in it.

Thanks,
Esther

Title: Re: problem in Charge pump design
Post by loose-electron on Dec 3^rd, 2006, 2:31pm

The charge pump structures that I have used are two switches, for the top, and two for the bottom. the top two control "pump up" and are complimentary. You direct the current into the loop filter, or you direct it to a voltage (created by the op-amp) that is close to the loop filter voltage.

The same thing happens with 2 switches in the "pump down" process.

As for charge injection compensation, see the attached picture. The geometry of the transistor functioing as the capacitor is half the size of the one working as the switch. Best way to implement is to use 3 transistors, 2 in parallel as the switch and the third as the capacitor.

Jerry

Title: Re: problem in Charge pump design
Post by ywguo on Dec 7^th, 2006, 10:58pm

Hi, Esther,

Don't worry the issue when the ref clock and feedback clock have large difference, because it is odd when a PLL is locked.

I don't understand the reason why do you split one period into two parts, period for bootstrapping and period and period for charge.

BG
Yawei

Title: Re: problem in Charge pump design
Post by Esther on Dec 13^th, 2006, 5:37pm

Thank you Jerry for your sharing.

Yawei

The reason I split clock period to chargeing period and bootstrapping period is that I care about the bootstrapping period is too short and not enough for opamp to pull the node voltage level to Vctrl before next chargeing switch turns on. I mean when clock ref and clock feedback have a almost 180 phase difference, the charging period is long but bootstrapping period is very short.

Thanks.
Esther

Title: Re: problem in Charge pump design
Post by jeffyan on Dec 21^st, 2006, 3:32am

Esther wrote on Dec 13^th, 2006, 5:37pm:

hi,
i don't think it is necessary to introduce a bootstrapping period.
first, i think, it will take a long time for the output of the op to follow the Vctrl, and not a transient process. so you need not a high bandwidth OP.
second, the added period, i think, will induce bad spur performance. :)
good luck
jeff