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Measurements >> Phase Noise and Jitter Measurements >> Synchronization of Timing Jitter in 640 MHz PLL.
https://designers-guide.org/forum/YaBB.pl?num=1165829267

Message started by phil_38 on Dec 11^th, 2006, 1:27am

Title: Synchronization of Timing Jitter in 640 MHz PLL.
Post by phil_38 on Dec 11^th, 2006, 1:27am

Hello All,

I need help about PLL relating to a 640 MHz PLL for Digital System. Indeed I have designed a PLL and succeded to simulate
the Long Time Jitter ( pll_lt_jitter.jpg below) under Eldo :). As you can see, jitter starts from 0, then increase because of jitter accumulation
due to the VCO and then the jitter stabilize because of the PLL Feedback. In this simulation, Reference Clock is jitter free.
But I don't know exactely what data I can extract from this simulation. Indeed, Reference Clock is at 20 MHz and I think that every
( 1 / 20 MHz ) s the PLL loop is re synchronized by the input reference. That would mean that Jitter would return to zero every ( 1 / 20 MHz ) s.
You can observe the kind of scheme that I have in mind in next message in file pll_lt_jitter2.jpg.

If this is true, from Long Time Jitter PLL simulation, I must extract Jitter @ ( 1 / 20 MHz ) = 50 ns, that is in my case equal to 15.46 ps.
If I am wrong, I must extract the Jitter when jitter is stabilized by the loop, that is Jitter = 32.56 ps ...

Can you help me and explain me what is the right strategy in order to extract the Timing Jitter ?

Thank you for you help by advance.

Regards, Phil.

Title: Synchronization of Timing Jitter ( file 2 ).
Post by phil_38 on Dec 11^th, 2006, 1:34am

Enclosed file pll_lt_jitter2.jpg relating to the previous question ...

Thanks !

Regards, Phil.