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Modeling >> Behavioral Models >> How to parameterize a string variable
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Message started by naone on Dec 15th, 2006, 11:41am

Title: How to parameterize a string variable
Post by naone on Dec 15th, 2006, 11:41am

I am trying to pass a string parameter into a verilogA file to use as the filename for an include file:

This is what I am trying but have syntax errors:

parameter filename = "incfile.txt"

`include filename


This does not work.  I also tried `include(filename) and this did not work either.

Any help is greatly appreciated.

Naone

Title: Re: How to parameterize a string variable
Post by Geoffrey_Coram on Dec 18th, 2006, 6:31am

I'm almost sure you can't do this at all; the problem is that `include is a preprocessor directive, handled by the compiler, well before anything else happens.

What are you trying to bring in in that include file, though?  Usually, include files tell the compiler something about how to compile; I guess you're trying to bring in some information for simulation, so you may be able to bring in the data another way (eg, $table_model).

-Geoffrey

Title: Re: How to parameterize a string variable
Post by jbdavid on Feb 9th, 2007, 3:13am

If you want to set some variables from the file, you can use

parameter string myFile = "default file name"
then
FH = $fopen( myFile, r): <- I don't remember how this works
var1 = $fscanf(FH);

Title: Re: How to parameterize a string variable
Post by Geoffrey_Coram on Feb 9th, 2007, 6:19am


jbdavid wrote on Feb 9th, 2007, 3:13am:
If you want to set some variables from the file, you can use

parameter string myFile = "default file name"


In what simulator?  I know it's in the LRM; I'm not aware of any simulators that support it yet ...

Title: Re: How to parameterize a string variable
Post by Andrew Beckett on Feb 22nd, 2007, 11:09am

Spectre does. I filed a PCR a while ago because string parameters weren't working in case statements, but that works now (in MMSIM60 and MMSIM61 versions for about a year). I just took the example I had with a case statement, and tried it out with fopen too - and that worked:


Code:
`include "discipline.h"
`include "constants.h"
module resexample (a,b);

inout  a,b;
electrical  a,b;
branch (a,b) resbr;
parameter real w=1u,l=1u,rsh1=1000.0,rsh2=400.0,rsh3=200.0;
parameter string rtype="M1";
real rval;
integer FH;

analog begin

   case (rtype)
   "M1": rval=rsh1*w/l;
   "M2": rval=rsh2*w/l;
   default: rval=rsh3*w/l;
   endcase
   $strobe("rtype is %s, rval is %g",rtype,rval);
   FH=$fopen(rtype,"w");
   $fstrobe(FH,"rtype is %s, rval is %g",rtype,rval);
   $fclose(FH);

   V(resbr) <+ rval*I(resbr);

end

endmodule


with this netlist:


Code:
//

r1 (1 0) resexample w=2u l=0.5u rtype="M2"
v1 (1 0) vsource type=dc dc=1

ahdl_include "resexample.va"

dc dc write=stuff.dc


It wrote out:

 rtype is M2, rval is 1600

both to the screen, and into a file called "M2".

Regards,

Andrew.

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