The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> VHDL-AMS >> How to simulate VHDL AMS models using cadence AMS
https://designers-guide.org/forum/YaBB.pl?num=1166422254

Message started by chviswanadh on Dec 17^th, 2006, 10:10pm

Title: How to simulate VHDL AMS models using cadence AMS
Post by chviswanadh on Dec 17^th, 2006, 10:10pm

Hello,

I need to verify a mixed signal design which has some components modelled in VHDL AMS.

Till now we were using verilog models. Can anybody help me out how to simulate these designs using Cadence AMS simulator

Thanks
Chviswanadh

Title: Re: How to simulate VHDL AMS models using cadence
Post by zhong on Dec 19^th, 2006, 11:13pm

Nothing special for VHDLAMS setup if you are familer with Cadence AMS Designer .
You can generate VHDLAMS in DFII cell view creation or compile text into DFII by ncvhdl -ams
then In HED , switch view binding to vhdlams view or whatever the view name you generated which include vhdlams contents . Then You are all set for kick off the simulation from this HED config. Please reference Cadence AMS user guide for how to kick off AMS simulation.

Title: Re: How to simulate VHDL AMS models using cadence
Post by chviswanadh on Dec 20^th, 2006, 4:28am

Hello zhong,

Thanks for the reply. I am able to create the symbol view of the VHDL AMS model and config view.
In the config view I selected the view list as entity since the vhdlams are related to this view.
But when I try to simulate, simulator is unable to recognise the port teminals as ports that are declared in the code.

Any comments on this.

Thanks
chviswanadh

Title: Re: How to simulate VHDL AMS models using cadence
Post by zhong on Dec 21^st, 2006, 12:49am

In HED swith to the view name defined in VHDLAMS architecture .
For example
entity my_block is
port(a1 , b1 : in std_logic;
y1 : out std_logic_ ;
end entity my_block ;

architecture behavior of my_block is
....
end architecture behavior

After you compile this into DFII via ncvhdl -use5x , you will see view "behavior" . switch to behavior view instead of "entity" view in HED .

Title: Re: How to simulate VHDL AMS models using cadence
Post by chviswanadh on Dec 21^st, 2006, 8:56am

Hello Zhong,

I have tried including the architecture name in the view list still it gives the same error.

Any comments on this

Regards
chviswanadh

Title: Re: How to simulate VHDL AMS models using cadence
Post by zhong on Dec 21^st, 2006, 7:20pm

chviswanadh ,
Not only in HED view list , In HED , instead of binding to "entity" , bind the cell to architecture name/view in HED cell view binding.

Please also check if ports in symbol are same as the ports declared in entity.

BTW, What is the specific errors you have seen ?

Zhong

Title: Re: How to simulate VHDL AMS models using cadence
Post by chviswanadh on Dec 24^th, 2006, 4:35am

Hello Zhong,

Thanks for the help. I have included vhdlams view in the HED viewlist.

Now it works fine.

Thanks
Chviswanadh