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https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> pll open loop phase noise simulation https://designers-guide.org/forum/YaBB.pl?num=1166576593 Message started by haeseonii on Dec 19th, 2006, 5:03pm |
Title: pll open loop phase noise simulation Post by haeseonii on Dec 19th, 2006, 5:03pm I originally posted this msg under rf simulator, but I think this fits better here. Thanks! :) I attached a very very simplified version of the ckt here. The DC source is to bias the transistor (represents the control voltage). I need to be able to see the effect of the noise of the resistor on the output with pss - pnoise simulation. What I observe right now is that the DC suppresses the resistor noise. Is there any way to do this? Thanks! --------------------------------------------------------------------------------- Hello, I need to simulate pll open loop phase noise in spectreRF (pss-pnoise). My circuit hasa CP - LPF -V2I - I2I - RO. I need to see what the effect of each component is to the phase noise. The problem that I am facing now, is that I need to set the control voltage to some value, but I am concerned that if I put a DC voltage source there, then it may suppress the effect of noise because the node is helt at a constant voltage. So, it would be great if someone can answer this, After PSS analyze the steady state of the circuit with all bias conditions, does pnoise calcultes the noise on top of the dc bias? or will the dc bias have effect on pnoise as well? Thanks! |
Title: Re: pll open loop phase noise simulation Post by smlogan on Dec 31st, 2006, 7:50pm Hi Haeseonii, I think I understand your concern. You are trying to determine the open loop noise of a VCO in a phase-locked loop and include the added noise of the "zero resistor " in series with the loop filter capacitor. With the DC voltage source across the resistor, the noise is not included as a result of the DC voltage source. I might suggest that placing the "zero resistor" in series with the voltage source might be a more realistic means of modeling the phase -locked loop. The voltage source represents the voltage on the largest capacitor of the loop filter. The zero resistor is in series with this capacitor in the actual circuit implementation. The ripple capacitor, assuming you are using one, is much a much smaller capacitor and will not effectively hold the control voltage as constant across the series combination of the "zero resistor" and loop filter capacitor. Hopefully, I've understood your question! Shawn |
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