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Design >> Mixed-Signal Design >> powerup/down time
https://designers-guide.org/forum/YaBB.pl?num=1166778535

Message started by dandelion on Dec 22^nd, 2006, 1:08am

Title: powerup/down time
Post by dandelion on Dec 22^nd, 2006, 1:08am

Hi,
I am designing a circuit which is used in the portable handset. I want to do the powerup and powerdown analysis, I wonder what is the rampup and rampdwon time should I select in simulation?

Also, There is also an enable signal in my circuit, which is assumed from the other chip in the system, e.g., a MCU.Same as above, what should I select the rampup and rampdown time should I select to do the enable/disbale analysis?

Thanks

Title: Re: powerup/down time
Post by ywguo on Dec 25^th, 2006, 1:43am

Hi,

The rampup and rampdown time depend on your voltage source, the bypass caps tied on VDD, etc. For simulation, I guess maybe 0.1us is enough. However, it needs very long simulation time if your circuit is very complex.

As the enable signal, I don't think its rise time or fall time are important.

BG
Yawei