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Design Languages >> Verilog-AMS >> Any CDR model by Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1167021549

Message started by neoflash on Dec 24^th, 2006, 8:39pm

Title: Any CDR model by Verilog-A
Post by neoflash on Dec 24^th, 2006, 8:39pm

Hope could view it as reference to write mine, thanks.

Title: Re: Any CDR model by Verilog-A
Post by Geoffrey_Coram on Jan 2^nd, 2007, 4:22am

What's a CDR?

Title: Re: Any CDR model by Verilog-A
Post by Frank Wiedmann on Jan 2^nd, 2007, 4:55am

Clock and Data Recovery, probably.

Title: Re: Any CDR model by Verilog-A
Post by jbdavid on Jan 20^th, 2007, 8:26pm

if you can use Verilog-AMS its probably better..
The main trick in my first one was to understand they type of CDR..
so I used a normal PFD for the "lock to reference" phase, when that is locked, the CDR gets a signal, that switches the control to the data channel Phase detector.
The model I have references the design of our IP vendor, so I can't share it. Just these general concepts.