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Design >> Analog Design >> PNP model
https://designers-guide.org/forum/YaBB.pl?num=1167035378

Message started by uncle_ezra on Dec 25^th, 2006, 12:29am

Title: PNP model
Post by uncle_ezra on Dec 25^th, 2006, 12:29am

I wrote a PNP power transistor model in spectre with the following parameters:
+ IS=1.2545e-14 BF=180 NF=1
+ VAF=68.28 IKF=0.375 ISE=1e-22
+ NE=1.18359 ISC=4.83798e-6
+ RB=0.331 RE=0.233
+TR=1e-8 TF=1e-10

I noticed that the beta of PNP goes negative at high temperature (120C) when the collector current is less than 150mA. Is there anything wrong with my model?

Title: Re: PNP model
Post by sheldon on Dec 25^th, 2006, 1:22am

Uncle Ezra,

First reaction, is that ISC seems high, ~1uA, since leakage
doubles every 10C, then the base-collector current at 120C
is several mA. Shouldn't be fatal but it is usual.

Best Regards,

Sheldon

Title: Re: PNP model
Post by uncle_ezra on Dec 25^th, 2006, 4:33pm

I see ... well thats the spice parameter ROHM provided for their power transistor and supposely works from -55 to 150C

Title: Re: PNP model
Post by sheldon on Dec 26^th, 2006, 6:56am

Uncle Ezra,

Can you share any additional information about how yoy are using the
pnp in your design? When I hook up a pair of PNP transistors as a simple
current mirror, at 120C, the Beta is about 140. It may also be that there
are diferences in the model defaults. Which simulator are you using?

Best Regards,

Sheldon

Title: Re: PNP model
Post by uncle_ezra on Dec 27^th, 2006, 12:51am

Basically I am using the PNP (off-chip) as my switch for my LDO design. So I have an opamp followed by a buffer (on-chip) which drives the PNP which then feedbacks to provide 1.8V supply voltage. The reason for not designing the whole regulator on-chip is because of high load current required.

As you said ISC seems high which is causing the beta to flip at high temperature. Not sure how accurate this figure is since I got this from the manufacture spice parameter. If I use the default value from spectre, which is 1e-13, beta is positive. Maybe because it is a power transistor the leakage may be large as compared to a regular PNP transistor.

Thanks

Title: Re: PNP model
Post by sheldon on Dec 28^th, 2006, 5:48am

Uncle Ezra,

There is one thing that is a little confusing about the model, the
forward Is is 1e-22 but the reverse Is is 4.8uA. This indicates a
very small emitter area with a huge collector area. The forward
characteristics don't seem consistent with a power transistor.
So the transistor may need more Vbe than expected.

Best Regards,

Sheldon

Title: Re: PNP model
Post by uncle_ezra on Dec 28^th, 2006, 5:02pm

Here is the link to the datasheet http://www.rohm.com/products/databook/tr/pdf/2sa1036k.pdf

Attached is the spice parameter provided by the manufacture

Title: Re: PNP model
Post by sheldon on Dec 29^th, 2006, 7:51am

Uncle Ezra,

What is the supply voltage for the LDO? If the pnp does not have enough
headroom, then the beta may have strange values. I did some simulations
and the drop-out voltage is about 0.7 for the transistor, see the attached
plots. BTW, the simulations are for a 1.8V LDO with 100mA of load current
and show the power supply being swept from 2.25V to 3V. The LDO does not
start acting like an LDO until the dropout voltage is greater than about 2.5V.

Also, my previous remark about it was incorrect. The IS of the transistor is
fine so the scaling should be correct. The low ISE just means that the process
is clean and the transistor has good low current beta.

Best Regards,

Sheldon

Title: Re: PNP model
Post by uncle_ezra on Dec 29^th, 2006, 5:34pm

Hello Sheldon,

Thanks, that picture makes sense. I am using a 3.3 V supply for a 1.8V LDO. The simulation just starts to behave strangely at high temperature (>100C) if load current <1mA. Basically higher load current is required at high temperature to ensure sufficient dropout across the pnp.

Thanks