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Design >> RF Design >> LC VCO’s sensitivity to supply voltage?
https://designers-guide.org/forum/YaBB.pl?num=1167137319

Message started by neoflash on Dec 26^th, 2006, 4:48am

Title: LC VCO’s sensitivity to supply voltage?
Post by neoflash on Dec 26^th, 2006, 4:48am

I am learning how to design a LC-VCO. Before I get hands dirty, I start to wonder a few things. One is the tank’s vulnerability to supply now. I think that there could be quite a few mechanisms to get power noise into output phase noise.

1. The junction capacitance could change over voltage supply, thus modulate the frequency.
2. I am not sure that if the LC-VCO doesn’t have a tail current and directly ground tail node, whether it is going to be more sensitive to supply noise?

Thanks,
Neoflash

Title: Re: LC VCO’s sensitivity to supply voltage?
Post by emad on Jan 1^st, 2007, 12:20am

Much of the frequency variation comes for the varactor side. Junction caps can modulate the frequency as well but with a much smaller gain. Therefore, varactor biasing needs to be designer very carefully and might very well require large on-chip capacitance.

As for the voltage-biased versus current-biased, the answer is yes, current biased VCOs are better wrt to pushing and this is predominantly because the exhibit less AM noise with supply variation. This, of course, if you bias the current source from a clean reference.

Title: Re: LC VCO’s sensitivity to supply voltage?
Post by neoflash on Jan 1^st, 2007, 12:51am

On the current (from nmos tail device) biased LC-VCO, where do you think we should reference "Vc" to?

VDD or GND?

In literature published in JSSCC 2005 Feb by "Sodini", he seems to reference the Vc to ground. However, I think it should be to VDD instead.

What is your opinion?

Title: Re: LC VCO’s sensitivity to supply voltage?
Post by ACWWong on Jan 1^st, 2007, 4:43am

hmm, depends on the values of the devices in the tank, core, Ctail, varactor/FET CV curves etc.. what i would do in this situation is simulate to get the answer. you can check how much a signal on ground or VDD pushes/pulls the VCO with both ground and vdd referenced loop filter. assuming noise on vdd or ground is small, using something like spectreRF pxf could be appropriate.

Title: Re: LC VCO’s sensitivity to supply voltage?
Post by emad on Jan 1^st, 2007, 10:05am

It depends on how you get your control voltage. You may be able to bootstrap the noise.

Title: Re: LC VCO’s sensitivity to supply voltage?
Post by rf-design on Jan 5^th, 2007, 3:19am

Typical a VCO have 3 supply ports.

VDD, VSS and SUB

The VDD could be regulated. All 3 are AM/FM sensitive. The nonlinear diffusion cap typical is the source of the conversion. Some tricks are to have a second set of diodes where the nonlinearity is stronger but the absolute cap contribution is lower. Then this set of second diodes are connected to other supplies. So if a supply voltage change the cap of the first set goes up and the cap of the second set goes down.