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Design >> RF Design >> Phase Noise in Ring VCO: Process scaling Issue?
https://designers-guide.org/forum/YaBB.pl?num=1167137643

Message started by neoflash on Dec 26^th, 2006, 4:54am

Title: Phase Noise in Ring VCO: Process scaling Issue?
Post by neoflash on Dec 26^th, 2006, 4:54am

Hi:

There is rumor saying that with the process going from .18 to .13 and 90nm, device noise is getting more and more severe in ring VCO design.

Previously, i guess that is .18um era, it is said that ring VCO design does not require a lot art to have low jitter. For 1GHz qudature CMOS ring VCO, it is easy to have jitter as low as 3ps (rms).

However, when I start to do some real work on 90nm, the phase noise is so huge that I can not skip huge passive noise filter and still have high timing jitter.

So, i hope those experienced designers in this field could comment on this trend.

Thanks,
Neoflash