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Design Languages >> Verilog-AMS >> transform stimuli from Spice
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Message started by Pavel on Dec 28^th, 2006, 3:08am

Title: transform stimuli from Spice
Post by Pavel on Dec 28^th, 2006, 3:08am

Hello

I received from my collegue stimuli file which he used in Spice for simulate our design.
It looks like this:

0.0000000000000 0
0.0000000001000 1
0.0000005901000 1
0.0000005902000 0
0.0000011802000 0
0.0000011803000 0
0.0000017703000 0
0.0000017704000 0
0.0000023604000 0
.
.
.

where left column is time in sec, right column is value to be assigned to a signal (say OUT).
I tried to transform it in veriog-ams using following approach

Code:

`include <stdio.h>
`timescale 100ps/10ps

module ISO_SEQUENCE (OUT);
`define EOF 0
output OUT;
reg OUT;

integer patterns;
integer bit_value;
real ftime;

initial begin
patterns = $fopen("./spice_stimuli.txt");
while(fscanf(patterns, "%f, %b", ftime, bit_value) != `EOF) begin
#(ftime*1e10) OUT = bit_value;
end
end
endmodule

Code couldn't be compiled as parser couldn't recognize <stdio.h> (I tried to find the path to stdio.h, but I failed)
Is there other approach or I should manually correct spice stimuli and then include its huge contents in my initial construction?

Regards.

Pavel.

Title: Re: transform stimuli from Spice
Post by Pavel on Dec 28^th, 2006, 7:44am

Problem is partially resolved.
Error was in syntax - fscanf in place of $fscanf and in input pattern.

But code doesn't work yet as it 's desired.
In folowing sequence
0.0000005901000 1
0.0000005902000 0
0.0000011802000 0

Signal, which receives read pattern, doesn't change to '0' at 0.0000005902000 s, but at next assignement - 0.0000011802000 s.
Why?
I tried to change timescale setting. It didn't help.

Regards.

Pavel.

Title: Re: transform stimuli from Spice
Post by Pavel on Jan 2^nd, 2007, 5:49am

Problem resolved.
I used blocking assignements in place of unblocking.

Regards.