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Measurements >> Phase Noise and Jitter Measurements >> VCO - divider phase noise/jitter
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Message started by Visjnoe on Jan 2^nd, 2007, 11:05am

Title: VCO - divider phase noise/jitter
Post by Visjnoe on Jan 2^nd, 2007, 11:05am

Hello

I'm puzzled about 2 reasonings about the phase noise/jitter relationship of a VCO and a subsequent divider (e.g in a PLL):

1. As stated in Ken's papers, a divider with N-stages sums (in a squared sense) the jitter from the VCO
-> Jit_divider = √N×Jit_vco

2. The relationship between the VCO and divider phase is given by:
Φdiv = Φvco÷N (1)

The VCO RMS jitter (time-domain) can be expressed as:
JitRMS,vco = Φvco÷(2π)×Tvco

Since Tvco = Tdiv÷N and since (1) is valid this expression can be converted to the jitter equation for the divider
(the 'N' terms cancel), showing that the VCO and divider jitter are equal!

Clearly, both reasonings contradict eachother, but which one is wrong and what is the error in the reasoning?

Thanks in advance!

Visjnoe

Title: Re: VCO - divider phase noise/jitter
Post by mg777 on Jan 17^th, 2007, 12:34pm

Case 1 is clearly the sum of independent Gaussian events. I'm guessing it refers to jitter contribution from the latch itself? Some set-up/hold business maybe.

Case 2 is intuitively correct. If I look at 'one out of N' bits, the placement accuracy of the N-th edge is independent of N. The jitter normalized to a UI will of course be reduced by the division factor, but not the p-p jitter.

M.G.Rajan
www.eecalc.com