The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> VHDL-AMS >> Procedural Simultaneous Statement
https://designers-guide.org/forum/YaBB.pl?num=1167842389

Message started by Daniel_Platte on Jan 3^rd, 2007, 8:39am

Title: Procedural Simultaneous Statement
Post by Daniel_Platte on Jan 3^rd, 2007, 8:39am

Hi all!

The VHDL-AMS language provides a feature "Procedural Simultaneous Statement" that is basically the same as Verilog-AMS's "Procedural Assignment". Unfortunately, AMS Designer and ADvance MS do not support the procedural simultaneous statement :'(.

Example (from a diode model):
--------------------------------------- BEGIN CODE SNIPPET --------------------------------------------------------

PROCEDURAL IS BEGIN
VD := VIN-VOUT-IIN*RS/AREA;
ID := GMIN*VD+AREA*(ISS*(-1.0+exp(0.181069E-2*VD*Q/K))-IBV*exp((-0.333167E-2)*(BV+VD)*Q/K));
CJ := AREA*CJO*iffunc1(VD);
END PROCEDURAL;

--------------------------------------- END CODE SNIPPET --------------------------------------------------------

The VHDL-AMS committee proposes to model this by using analog functions like this:

--------------------------------------- BEGIN CODE SNIPPET --------------------------------------------------------

TYPE QR IS RECORD
VDv : REAL;
IDv : REAL;
CJv : REAL;
END RECORD;

FUNCTION proceqs(
VINi : REAL;
IINi : REAL;
VOUTi : REAL;
IOUTi : REAL;
VDi : REAL;
IDi : REAL;
CJi : REAL;
dIDdti : REAL;
dVDdti : REAL
) RETURN QR IS
VARIABLE VINv : REAL := VINi;
VARIABLE IINv : REAL := IINi;
VARIABLE VOUTv : REAL := VOUTi;
VARIABLE IOUTv : REAL := IOUTi;
VARIABLE VDv : REAL := VDi;
VARIABLE IDv : REAL := IDi;
VARIABLE CJv : REAL := CJi;
VARIABLE dIDdtv : REAL := dIDdti;
VARIABLE dVDdtv : REAL := dVDdti;
BEGIN
VDv := VINv-VOUTv-IINv*RS/AREA;
IDv := GMIN*VDv+AREA*(ISS*(-1.0+exp(0.181069E-2*VDv*Q/K))-IBV*exp((-0.333167E-2)*(BV+VDv)*Q/K));
CJv := AREA*CJO*iffunc1(VDv);
RETURN (vdv, idv, cjv);
END;

[...]

(VD, ID, CJ) == proceqs(VIN, IIN, VOUT, IOUT, VD, ID, CJ, dIDdt, dVDdt) TOLERANCE "Current";

--------------------------------------- END CODE SNIPPET --------------------------------------------------------

Unfortunately, the topology checker of AMS Designer counts this simultaneous statement as one equation (instead of three) and refuses to simulate the model...

Does anyone have experience how to work-around this problem? Are there simulators supporting the proc. sim. stat. or plans to realize the language construct?

Thanks in advance for any help.

Cheers,
Daniel

P.S. Complete VHDL-AMS code is attached

Title: Re: Procedural Simultaneous Statement
Post by Geoffrey_Coram on Jan 4^th, 2007, 11:16am

I'm not an expert in VHDL, but: shouldn't the model compute charge rather than capacitance?

Code:

-ID-0.115E-7*dIDdt+IIN-CJ*dVDdt == 0.0 TOLERANCE "Current";

Title: Re: Procedural Simultaneous Statement
Post by Daniel_Platte on Jan 5^th, 2007, 12:53am

You're right, charge conservation is not ensured within the posted model. Anyway, the diode model only provides the basis for my question on the VHDL-AMS realization of proc. statements. Is anyone using VHDL-AMS for device modeling purposes?

Title: Re: Procedural Simultaneous Statement
Post by Geoffrey_Coram on Jan 18^th, 2007, 4:25am

Daniel_Platte wrote on Jan 5^th, 2007, 12:53am:

Is anyone using VHDL-AMS for device modeling purposes?

I hope not! I've been presenting tutorials on why Verilog-A is the right language for device modeling. :)

Seriously, though, there were a few groups that used to; some of them were connected with Prof C-J Richard Shi at U. Washington, whose MCAST model compiler would convert "VHDL-A" models into Spice C code. (Note that "VHDL-A" isn't a standard, and I guess is defined in some sense by what MCAST can do ...)

Title: Re: Procedural Simultaneous Statement
Post by abhi_kolpekwar on Jan 18^th, 2007, 2:59pm

+ Unfortunately, the topology checker of AMS Designer counts this simultaneous statement as one equation (instead of three) and refuses to simulate the model...

I am assuming you are refering to a compile time error about solvability check. You can use a ncvhdl option "-nosolvecheck" to get around this error. This disables the solvability check by the compiler.

AMS designer support user defined functions to help write device models. However, it does not support analog records yet. Your example uses analog records.