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Design >> RF Design >> Crystal Oscillator Simulation
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Message started by ic_engr on Jan 3^rd, 2007, 9:52am

Title: Crystal Oscillator Simulation
Post by ic_engr on Jan 3^rd, 2007, 9:52am

Hello,

I have a circuit for crystal oscillator which I am able to simulate using ic=2uA for the inductor. The Lm=69mH and Rm is 40Ohms. Therefore, the Tau=1.28msec approx.

The ciruit simulates properly at 30C and 60C.

The problem is that when I simulate at -20C the oscillations die. Is this expected. ?
I also simulated the oscillator without crystal and noted that at 200msec, the gm of the amplifier NMOS at -20C is 12 times lower than at the 60C. However, after 1 second the gm settles to the final value very close to the gm at 60C. The reason for long time constant for the gm is due to the way the circuit is designed.

What is the implication of having long time constant for the gm of the circuit although the crystal time constant is only 1.28msec. Will the circuit start-up eventually at -20C.

How does the tau of the Crystal and tau of the circuit implicate the operation at start-up.

Any suggestions.

ic_engr

Title: Re: Crystal Oscillator Simulation
Post by topquark on Jan 4^th, 2007, 12:11am

Hi,

I'm intrigued by this claim:
"...the gm of the amplifier NMOS at -20C is 12 times lower than at the 60C"

As I understand, gm of MOS is a function of μ and V_t which are the only temperature variables!
μ decreases with temp. while V_t increases with temp.
So, effectively gm(-20C) > gm(60C)

Am I right?

Title: Re: Crystal Oscillator Simulation
Post by ACWWong on Jan 4^th, 2007, 2:23am

It is normally the case to boost gm initially before reducing it back to the steady state level, this is to enable robust start up, but low current consumption when fully oscillating. So a circuit which actively (current starves ?) has a very low gm to start with is very strange... can you go into the reason this design choice was made ?

Anyway low temperature is always were one worries about the startup, especially with a dozy crystal.... but i would guess that so long as you have enough negative resistance to overcome the net losses eventually, then the oscillator will EVENTUALLY start. Often depending on your application, EVENTUALLY isn't really good enough...

Title: Re: Crystal Oscillator Simulation
Post by ic_engr on Jan 4^th, 2007, 7:49am

Okay,

The design was done by someone else. The reason I am looing into it is because we are having two issues at tests:

1. Some devices are taking very long to start-up
2. Some device fail to start-up.

I got involved to review the design and what I noted is that the design was not conventional. i.e usually we have a feedback resistor between the Drain to gate of the ampliifer to bias the amplifier in the operating region. What the designer did is:

connected the large feedback resistor (260k) through a diode connected BJT (NPN with Base and Collector shorted to gate and emitter to one terminal of the feedback resistor) to the gate of the NMOS transistor. So at start-up when all the nodes are sitting at zero, the current trhough the feedback resistor to charge the gate of NMOS close to VTn is in picoamps due to the reverse bias diode in the path. So the design is relying on the IS current of the diode to charge the gate of the NMOS to VT. Why was it done no one knows. Could have been for temperature compensation with the varactors that are being used.?

So when I start-up the simulation the gate voltage takes long time to reach VTN and therefore GM is not going to be the right value. I ran simulation at room temerature which worked fine. I later also tried the same simulation at room temperature but with NPN having a slow corner model. What I noted is that the oscillation died.

So I am not sure, will I see tru falilures or delay on start-up or both ?

ic_engr

I also

Title: Re: Crystal Oscillator Simulation
Post by rf-design on Jan 5^th, 2007, 3:12am

Do not think about this too long. It would be a wast of your time. The circuit is simply missconstructed. It is possible a very first user error because the simulator would show a DC bias condition where the gate voltage is already reached. I have looked into SW solution do checks like this automatic in 80s but there was no interest. Today the review resources are lacking and 500k$ masks are put in waste for starter errors.

Thats life >:( ::)

Title: Re: Crystal Oscillator Simulation
Post by ic_engr on Jan 10^th, 2007, 9:30am

Well, I started simulation with all nodes set to zero. So I do see the gate voltage is rising to about VTN in 1sec. I noted the total lumped capacitance of MIM caps and the CGG of NMOS = 7pF connected to the gate of the NMOS. The charging current trhough the diode connected NPN is 400fA (femto Amps). So theoretically its about 7 seconds.

I do have three out of 4 wafers clocking properly. But there is one wafer on which all 3000 parts do not seem to start the oscillator or may be they require the tester to wait longer time.

The question is would the femto amps of current eventually charge the gate of the device gate leakage is going to keep the node always near zero.?

ic_engr

Title: Re: Crystal Oscillator Simulation
Post by rf-design on Feb 4^th, 2007, 2:41pm

You have to take the result as it is. Waiting longer is a good advise. But be shure it is only useful for characterisation. I hope that these kind of errors are not get in contact with customers or consumers.