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Design >> Mixed-Signal Design >> ADC clock jitter specification
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Message started by Visjnoe on Jan 4^th, 2007, 5:22am

Title: ADC clock jitter specification
Post by Visjnoe on Jan 4^th, 2007, 5:22am

Dear all,

the detrimental effect of clock jitter on ADC (flash, delta-sigma...) has been described in literature with well know equations.

However, each of these papers talks about 'clock jitter' in a general sense, without specifying which jitter is actually meant (edge jitter, period jitter, cycle-to-cycle jitter, long term jitter...)

Now, I think that for the ADC, edge jitter is the relevant specification, but I'm doubting between edge jitter and period jitter.

Has anyone a clear view on this?

Kind Regards

Peter

Title: Re: ADC clock jitter specification
Post by carlgrace on Jan 4^th, 2007, 6:40am

Peter,

The different "kinds" of jitter you mention are really different ways of looking at the same thing. Jitter is just a consequence of the period of the clock having some amount of variability. Long-term jitter is not an issue, because the clocks are generated in a feedback loop (some kind of PLL usually) so the average period over time is constant. What is troublesome from an SNR standpoint in an ADC is the instantaneous variations between periods. So, I would call edge jitter, period jitter and cycle-to-cycle jitter synonyms.

What matters to an ADC designer is where the clock edge is relative to where it should be. If you think about it, you'll see that shortening the period of the clock by a small Δt is the same as moving the sampling edge a little bit to the left of the ideal sampling instant on the time axis. So, it is probably most intuitive to think of "edge jitter", but they are really all the same thing.

Incidently, since jitter is a random process, its rms value is usually what is specified. Keep in mind jitter (usually) has a Gaussian PDF so sometimes the instanteous jitter is significantly larger than the listed rms value. This can be important if you care about individual sample errors, such as in a digital comms application. It isn't so much of a bother if you are just interested in the waveform, for example if you are digitizing audio or video. If this is an issue for you, you'll need to see a digital comms book for the impact sampling time errors have on BER.

Regards,
Carl

Title: Re: ADC clock jitter specification
Post by Visjnoe on Jan 6^th, 2007, 3:33pm

Carl,

thanks for your view on the jitter specification of the ADC.

The topic of random jitter and its RMS value is interesting: what is the actual jitter specification of the CLK of an ADC?
I agree that in case of random, Gaussian noise, one should consider the RMS value (except for applications where individual samples are important).

However - and this can certainly be the case - if your ADC CLK contains a deterministic jitter component DJ , e.g. low-frequent sinusoidal jitter,
would the jitter used in the well-known equation for the ADC be 0.5*DJ_pp? I guess not, since the derivation of the equation was made for RJ?!

But in reality, your ADC CLK will contain DJ and RJ jitter, with the TJ (Total Jitter) being given by:
TJ = DJ+n*RJ with n = 6 (e.g.) and DJ expressed in p-p and RJ expressed in RMS.

Assume you know your ADC CLK has such a profile, how would you calculate the 'dt' that is used in the ADC jitter equation?
Personally, I think dt = 0.5*DJ+n*RJ in case DJ is high-frequent and dt = n*RJ in case DJ is low-frequent and reality is in between...

Kind Regards

Peter

Title: Re: ADC clock jitter specification
Post by carlgrace on Jan 9^th, 2007, 8:42am

Peter,

Your thoughts regarding deterministic jitter are interesting. I haven't personally seen a situation where such DJ was significant. It would seem to me that significant DJ would indicate a poorly functioning PLL in the clock generation block. Could you tell me some more detail about your situation that is causing DJ to be a problem? Off hand, I cannot think of a practical situation where the dominant jitter mechanism would be deterministic.

I haven't done any analysis, but intuitively I would imagine that DJ would be analogous to timing mismatch in a time-interleaved ADC. So, the result would be sidebands in the output spectrum. The amplitude of the sidebands would be related to the frequency of the DJ, but if it were low frequency I would imagine they would not be significant (by "low frequency" I mean significantly less than F_s).

Regards,
Carl

Title: Re: ADC clock jitter specification
Post by Visjnoe on Jan 9^th, 2007, 11:20am

Carl,

I have been thinking about the ADC CLK jitter specification and it's fair to say that the jitter will contain low-frequency and high-frequency components. I now think that is the most important distinction, not DJ/RJ.

Now let's turn our attention to the ADC CLK jitter requirement: all papers just mention 'dt', without describing the nature of the jitter.
Statements like 'ADC CLK Jitter should be better than 10ps' etc. are made.

Given a certain CLK (e.g. coming from a PLL), one should now where to start/stop the phase noise integral...effectively choosing which low-frequency components of the jitter to disregard!
I think it is easy to understand that the high-frequency jitter is important for the ADC, since it affects the difference between 2 consecutive periods.
But a low-frequent jitter component will reach its pk-pk value over e.g. several ms...for a MSps ADC, the periods where it reaches its min/max value are very far apart...so I would think it is of no importance.

Peter

Title: Re: ADC clock jitter specification
Post by Visjnoe on Jan 9^th, 2007, 11:22am

Title: Re: ADC clock jitter specification
Post by ywguo on Jan 10^th, 2007, 11:04pm

Hi, Peter and Carl,

That is a really interesting topic. I have been thinking it over from I studied ADC and PLL. I was perplexed at the begining. Deterministic jitter, random jitter, long term jitter, short term jitter, period jitter, cycle-to-cycle jitter .... There are a lot of terms for those guys who design a PLL. However, the jitter requirement for ADC is generally stated like jitter or rms jitter. So Peter said as below.

Quote:

Now let's turn our attention to the ADC CLK jitter requirement: all papers just mention 'dt', without describing the nature of the jitter.
Statements like 'ADC CLK Jitter should be better than 10ps' etc. are made.

Obviously, there is a gap between the engineers who design PLLs and those who design ADCs. However, the definitions of jitter are so complex that I will clarify here before I talk about the jitter requirement for ADC.

Why Peter said DJ and RJ Carl said edge jitter, period jitter, cycle-to-cycle jitter?

In fact DJ and RJ are not terms used for a clock generator, but for a transmitter in data communication like LVDS or Serdes. The output of a transmitter is binary stream, not a clock. :) The DJ and RJ of a transmitter is often tested using a Pseudo Random Binary Stream (PRBS) source. So the DJ is composed of sinusoidal jitter (low frequency), data dependent jitter (ISI), and Duty Cycle Distortion. They are caused by some deterministic source, often strongly related to the circuit topology. We care about pk-pk value of DJ. RJ is due to the clock source in the transmitter. It makes the edge of the binary stream goes ahead or lag the ideal point randomly. It is mainly caused by thermal noise. The measured pk-pk value of RJ depends on how long you measure the output of a transmitter. So we measure its rms value. Then according to the required BER, we decide how many times rms value of RJ is added with DJ. So we have the formula TJ=DJ+n*RJ. Normally, n is not equal to 1.

The long term-jitter, short-term jitter, period jtter are used to characterize a clock. For clock of ADCs, I agree with Carl on the statements below.

Quote:

Jitter is just a consequence of the period of the clock having some amount of variability. Long-term jitter is not an issue, because the clocks are generated in a feedback loop (some kind of PLL usually) so the average period over time is constant. What is troublesome from an SNR standpoint in an ADC is the instantaneous variations between periods. So, I would call edge jitter, period jitter and cycle-to-cycle jitter synonyms.

Furthermore, we often lock the phases of clock source and signal source when testing ADCs, thus the long term jitter is not important here.

Here I want to discuss cycle-to-cycle jitter and period jitter. Some literature use both names as synonyms. However, sometimes cycle-to-cycle jitter is not period jitter. For a spread-spectrum clock, which is often used on a PC motherboad to meet FCC EMI requirment, cycle-to-cycle jitter is the differnece between two consecutive cycles.

Any comments are welcomed.

Yawei

Title: Re: ADC clock jitter specification
Post by Visjnoe on Jan 10^th, 2007, 11:57pm

Hi Yawei,

your observation was correct, my background lies indeed in Serdes/LVDS design ;)

Now, concerning the CLK jitter requirement of the ADC, your reasoning why we only care about the random, thermal noise has convinced me. I think you are right to state that e.g. data dependent jitter is no issue for an ADC CLK.

However, there is 1 caveat: there can be other than random jitter introduced onto the CLK: namely by low-frequency/sinusoidal jitter on the supply that is used for the CLK buffers.

But apart from this component, I can agree on the thermal noise statement. That however still leaves us with the question of the boundaries of the integral of the phase noise: what is the lower bound that one should take?

Kind Regardsd

Peter

Title: Re: ADC clock jitter specification
Post by ywguo on Jan 11^th, 2007, 12:18am

Hi, Peter,

I have never thought of the jitter introduced to the clock as what you said. I think you are right. Any interference will appears at the FFT plot of the ADC output.

The low bound of the integral of the phase noise is determined by the measuring time. If the measuring time is T, the low bound f_low=1/T. Maybe that is enough.

Best regards,
Yawei

Title: Re: ADC clock jitter specification
Post by Visjnoe on Jan 11^th, 2007, 7:32am

Dear Yawei,

I agree with the statement that if you want to see the low-frequency jitter component of frequency 1/T during measurements, you should at least measure for T time to observe its full pk-pk value.

But what we're really interested in is the low-frequency jitter components that we have to take into account for the CLK jitter specification (this is not related to our measurement strategy): I believe that there might be very low frequency components in the jitter spectrum (e.g. 1kHz), but they do not effect 2 consecutive CLK periods (given a high frequency CLK, e.g. 10MHz) and thus (to my opinion) do not influence the ADC noise floor. Note that I am not 100% certain about the last statement.
This leaves us with the question: from where on in the frequency band do we take jitter components into account?

Kind Regards

Peter

Title: Re: ADC clock jitter specification
Post by ywguo on Jan 11^th, 2007, 7:25pm

Hi, Peter,

Maybe I didn't explain clearly. I mean that we should integrate from f_low=1/T if measureing ADC for time T.

For eg., for a 8192 points FFT plot of a 10MS/s ADC, the measuring time is less than 1ms. So the low frequency components in a jitter spectrum less than 1KHz is not necessary to be taken into account.

Usually I have only very simple oscillascopes. So I measure period jitter directly. I have never think about the jitter spectrum when I test ADCs. That is very different from designing and testing a SERDES/LVDS or SDH transciever, where the jitter spectrum/ jitter tolerance are very important.

Yawei

Title: Re: ADC clock jitter specification
Post by mg777 on Jan 14^th, 2007, 12:40pm

How important is the aperture jitter to your sampling system? Obviously very much if you're building an oscilloscope. But take two other cases, both with signals involving substantial crest factors: (i) audio, and (ii) an OFDM waveform (as in WiFi).

In the audio case the hoary chestnut is that the human ear is more sensitive to magnitude than phase, but this has been questioned (see for example www.silcom.com/~aludwig/Phase_audibility.htm).

In the case of OFDM type waveforms, the ballgame is totally different. Jitter-induced interchannel interference can impact multiple parameters such as EVM, BER, and spectral regrowth. A recent thesis at Georgia Tech has addressed some of these issues: http://etd.gatech.edu/theses/available/etd-03162006-155352/unrestricted/onunkwo_uzoma_200603_phd.pdf

M.G.Rajan
www.eecalc.com