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Design >> High-Speed I/O Design >> LVDS chain jitter analysis
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Message started by Visjnoe on Jan 7^th, 2007, 4:26am

Title: LVDS chain jitter analysis
Post by Visjnoe on Jan 7^th, 2007, 4:26am

Dear all,

let's assume a chain of N LVDS TX/RX stages and assume that the TJ (Total jitter) for one LVDS TX/RX stage equals:

TJ_stage = DJ +N*RJ

with DJ = Deterministic Jitter (expressed in ps,pk-pk), including data-dependent jitter, sinusoidal jitter,...
and RJ = Random Jitter (expressed in ps, RMS), caused by device noise
and n = 6 (e.g.) or 3 or 9 or...depending on observed characteristics of the Gaussian process (RJ)

My question is: can an approximate formula for a chain of such LVDS TX/RX be constructed?

If there would be only RJ, the answer would be:
TJ_Chain = sqrt(N)*TJ

It is the DJ that has me confused: I don't think it adds up in a sqrt(N) sense since the noise is correlated, but I'm not sure how to assess it further on...

Thanks in advance!

Peter

Title: Re: LVDS chain jitter analysis
Post by mg777 on Jan 20^th, 2007, 12:34pm

Assume the DJ is caused by the intersymbol interference (ISI) due to a cable's frequency roll-off. If I cascade two such channels I expect faster roll-off and hence more DJ. So I'm guessing (in this case) that the DJ will accumulate slowly to start with - the eye will remain quite open, but as the ISI gets bad the eye will close fast and the DJ will take off. Almost a unit step like behavior u(N-N_c) where N_c is some critical number of stages in the cascade.

M.G.Rajan
www.eecalc.com

Title: Re: LVDS chain jitter analysis
Post by fonseca.ha on Mar 7^th, 2007, 4:34am

Hi Peter,
Does each stage of the lvds chain re-generate the signal? If so, I think that DJ should only have an impact on each stage locally. As I see it the DJ at the end of the chain should come from the DJ of the last stage. The impact of the DJ of the other stages would appear in the system as an increase in the BER.

Regards,
Humberto

Title: Re: LVDS chain jitter analysis
Post by smlogan on Aug 11^th, 2007, 8:02pm

Hi Peter,

All good questions! I'll provide my two cents on the issue.

First, I believe the following approximations may only be used if the LVDS buffers have sufficient bandwidth relative to the random and deterministic jitter components. Specifically, as the total jitter causes the eye to be closed, the waveform presented to an LVDS buffer may not adequately achieve the required logic high and low level amplitude. In this case, one must examine the noise margin of the series of buffers. Clearly, at some level of total jitter, the series connection of buffers will not produce the input waveform accurately - i.e., a logic high or low at the input will not produce a logic high or low at the output of the chain. I think by examining the noise margin of the series connected buffers, one may estimate what level of total jitter must be examined in more detail.

If, however, the total jitter is not close to a level that impinges on the noise margin, I think the following approximations might be in order.

In the case of random jitter, which should be a minor contributor, I would expect that over the frequency range of interest, for N LVDS buffers the output random jitter may be obtained by the sum of the squares.

sigma_RJtotal = power(N*power(sigma_rj,2),0.50)

This is an approximate relationship as long as the same integration period is used for the random jitter for all buffers - as well as the output jitter.

For deterministic jitter, indeed, each LVDS buffer will contribute jitter and the total peak-to-peak jitter may be obtained as the sum of the deterministic jitter added by each individual buffer - if each buffer contributes the same amount DJpp_per_buffer.

DJpp_total = N * DJpp_per_buffer

where: DJpp_per_buffer = Peak-to-peak DJ for each buffer in the chain

However, as the capacitive load on the buffers may vary, it is highly likely you will need to consider the DJ contribution of each buffer separately and sum the peak-to-peak of each buffer. The DJ will be a function of buffer load.

I realize this is different than the method suggested in the prior reply. If that hypothesis were correct, one could simply place an infinite number of buffers in series and only see an output deterministic jitter representative of a single buffer. However, in reality, despite the fact that a buffer may improve the transient response of a waveform, its output edges at the threshold are modulated. Intuitively, as an example, if the deterministic jitter is caused by a modulation of the power supply, in effect the propagation delay of the buffer is modulated. Each buffer has its own propagation delay that is modulated and hence the total modulation is the sum of the modulation of each buffer - not the modulation of just the last buffer in the chain.

Feel free to comment - and I hope I've managed to interpret your question correctly!

Shawn

Title: Re: LVDS chain jitter analysis
Post by ywguo on Aug 14^th, 2007, 7:56pm

Hi Shawn,

It is such an interesting topic, :) while it is quite perplex.

First, what Humberto mean is that the DJ impacts locally only if the LVDS chain re-generate the signal. In other word, if the LVDS stage has clock and data recovery, the DJ does not propagate to the next stage. I think that is correct.

Second, if the LVDS chain does not re-generate the signal, I almost agree with you. Sure the DJ is quite complex, too. For ISI and duty cycle distortion, what you proposed is quite right. But for period jitter, it is hardly to sum the period jitter of each stage because they are strongly correlated if they are modulated by the same interference/signal. That is possible if all the stages are in one system.

Best regards,
Yawei

Title: Re: LVDS chain jitter analysis
Post by smlogan on Aug 15^th, 2007, 3:21pm

Hi Yawei,

Thanks for your response! Phase jitter questions are quite interesting - as are the various comments and suggestions!

I understand, now, what Humberto was suggesting. From the nature of Peter's initial question, I assumed he was sending a data or clock through a series of LVDS buffers with out any intervening clock and data recovery circuits.

As you correctly noted, the presence of an intervening clock and data recovery element will impact the resulting random and deterministic jitter components due to its bandwidth limiting effect. I was interpreting Humberto's term of "regenerating" to simply mean "amplifying". Sorry Humberto, for my mis-reading of your response!

My approximations were aimed at estimating time interval error after a chain of (non-regenerative) buffers. If one is examining the impact of a series connection of non-regenerative buffers on period jitter (i.e., the differences in positive or negative edge transitions), there will be a frequency dependence and the expressions I provided are not accurate.

Thank you for your close reading and comments.

Shawn