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Design >> Analog Design >> cmos analog.. all transistors always in saturation
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Message started by Alm on Jan 8^th, 2007, 9:08am

Title: cmos analog.. all transistors always in saturation
Post by Alm on Jan 8^th, 2007, 9:08am

Hello,

I am sizing a two stage opamp with a fixed given topology. I need to vary Widths of various transistors to make the circuit meet some performance criterion.

My question is a general design question.

We generally bias transistors in the saturation region to have a good gm.

Is it a safe assumption that for most cmos opamps, all the transistors will be biased in the saturation region?

Thanks.

Alm P.

Title: Re: cmos analog.. all transistors always in satura
Post by ACWWong on Jan 8^th, 2007, 3:40pm

Yes, generally MOS devices in two stage opamps are biased in saturation. Major reasons are good output impedance, historic, saturation is a relatively well defined operating condition etc.
But there are many (albeit minority) cases, especially at low power and low voltage, where MOS devices in opamps may not be biased in saturation (i.e in weak inversion, triode etc.).
So it might not be completely safe to assume all devices in any MOS opamp schematic are in saturation.
cheers
aw

Title: Re: cmos analog.. all transistors always in satura
Post by vivkr on Jan 11^th, 2007, 1:07am

ACWWong wrote on Jan 8^th, 2007, 3:40pm:

Hi AW,

I notice with interest how you demarcate "saturation" from "weak inversion". I would say that the two are not mutually exclusive. In fact, if you
are designing opamps for high Gm (obviously), then the input devices of the opamp are unlikely to be in strong inversion as the Gm of a MOS is quite
poor in really strong inversion but gets better towards moderate and weak inversion. So, for switched-cap applications, your opamp probably has input
devices which are in saturation but also in moderate inversion. The only circuits where one might want to really bias all opamps in truly strong inversion might be high-speed continuous-time circuits where slewing is not allowed in the opamp.

I would suggest that we all be more careful about not mixing up saturation and linear region with strong inversion and weak inversion.

Regards
Vivek

Title: Re: cmos analog.. all transistors always in satura
Post by ACWWong on Jan 11^th, 2007, 2:45am

vivkr wrote on Jan 11^th, 2007, 1:07am:

I would suggest that we all be more careful about not mixing up saturation and linear region with strong inversion and weak inversion.

Agreed. The term "weak inversion" should correctly be omitted from my original post. Thanks vivkr for pointing out my lapse in correct terminology ::)

Title: Re: cmos analog.. all transistors always in satura
Post by Croaker on Jan 12^th, 2007, 1:50pm

ACWWong wrote on Jan 11^th, 2007, 2:45am:

vivkr wrote on Jan 11^th, 2007, 1:07am:

I would suggest that we all be more careful about not mixing up saturation and linear region with strong inversion and weak inversion.

Agreed. The term "weak inversion" should correctly be omitted from my original post. Thanks vivkr for pointing out my lapse in correct terminology ::)

For anyone following along, a weak inversion MOSFET saturates for Vds greater than a few Vt (kT/q).

To answer the original question, you usually bias the MOSFETs in saturation for high gm and ro...high gain. Plot an inverter or common source transfer curve and note that the high gain region occurs when the FETs are saturated.

Title: Re: cmos analog.. all transistors always in satura
Post by avlsi on Jan 23^rd, 2007, 2:45am

HI,

These are the rules of thumb I came across during my design.

1. Weak Inversion (W.I.)- High Gain, Low Power (current consumption), Low Bandwidth
2. Moderate Inversion (M.I.)- Good Gain(<W.I), Moderate Power(>W.I.), Moderate Bandwidth (>W.I.)
3. Strong Inversion ( S.I.) - Low Gain (< M.I.), High Power(>M.I.), High Bandwidth ( > M.I.)

Whenever you design, decide which region of operation is best suited taking the above table into account.

W.I. has a potential problem, if the drain source voltaeg across MOSFET is not greater than Thermal Voltage, the device is totally off and this should be taken care by ensuring VDS> 4 . VThermal

Title: Re: cmos analog.. all transistors always in satura
Post by Alm on Jan 23^rd, 2007, 6:27am

Many thanks to everyone for their comments. They were all very helpful.

-Alm

Title: Re: cmos analog.. all transistors always in satura
Post by Croaker on Jan 25^th, 2007, 7:17am

avlsi wrote on Jan 23^rd, 2007, 2:45am:

For any process, it's interesting to plot gm/Id (transconductance efficienty) vs. Vgs and fT vs. Vgs. Superimpose these graphs on the same plot and you'll quickly see your rules of thumb right there on the plot. For those who don't get around to it, the plot is roughly X-shaped, where gm/Id is high for low Vgs and fT is high for high Vgs. Right around moderate inversion the plots cross over so you get a good balance between gain, power, and speed.

Title: Re: cmos analog.. all transistors always in satura
Post by SRF Tech on Jan 25^th, 2007, 8:14pm

My design approach, especially when dealing with a new process is to begin by doing exactly what Croaker recommends. One of the beautiful aspects of plotting the "efficiency" and "ft" as suggested is that it is independent of width dimensions; which also happens to be a great tool when comparing different processes for design considerations.
-SRF Tech