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Design Languages >> Verilog-AMS >> porting verilog-A code from unix to windows in hsp
https://designers-guide.org/forum/YaBB.pl?num=1168397650

Message started by robertosung on Jan 9^th, 2007, 6:54pm

Title: porting verilog-A code from unix to windows in hsp
Post by robertosung on Jan 9^th, 2007, 6:54pm

Hi,
I have a verilog-A code that runs on unix version of hspice. But it doesn't run in
windows xp even though I have the hsp-vacomp license. The file name is
tx_datagen.va and it complains that tx_datagen.cml is not found. SO I tried
to compile it in the command prompt window.

hsp-vacomp -V 2 -W 2 -I ..\ -o tx_datagen.cml -M tx_datagen.va

It gave me the following warnings

Warning: module 'tx_datagen', memory state: 'sd_future'

to all of the following variables

real voutodd, voutoddnext, voutodd_1;
real voutoddb, voutoddbnext, voutoddb_1;
real voutoddlead, voutoddlag, voutoddlead_1, voutoddlag_1;
real voutoddblead, voutoddblag, voutoddblead_1, voutoddblag_1;
real sd_past, sd_now, sd_future;
real tap111lead, tap111lag, tap110lead, tap110lag;
real tap101lead, tap101lag, tap100lead, tap100lag;
real tap011lead, tap011lag, tap010lead, tap010lag;
real tap001lead, tap001lag, tap000lead, tap000lag;

Is there a syntax change between the two operating systems?

Thanks in advance

Title: Re: porting verilog-A code from unix to windows in
Post by Geoffrey_Coram on Jan 10^th, 2007, 10:04am

Do you have the same version of HSpice installed on both platforms? It sounds like maybe you have a newer (smarter) version installed on unix.

Title: Re: porting verilog-A code from unix to windows in
Post by robertosung on Jan 10^th, 2007, 11:56am

Actuall, I am using the same hspice version in both unix and windows which is
2006.09
It doesn't give any errors other than the warnings about memory state.
But it doesn't generate a cml file.

Thanks, Roberto

Title: Re: porting verilog-A code from unix to windows in
Post by Geoffrey_Coram on Jan 11^th, 2007, 4:02am

I've never used HSpice on Windows, so I can't help much. Just a few thoughts.

Does the .val (verilog-a log) say anything?

Have you ever successfully compiled a VA model on Windows? Does it usually put them in a model-cache directory? Is there anything there, and/or is the directory writable? Do you have all the `include files (disciplines.vams, constants.vams)?