The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Simulate to estimate process ft https://designers-guide.org/forum/YaBB.pl?num=1168450458 Message started by ic_engr on Jan 10th, 2007, 9:34am |
Title: Simulate to estimate process ft Post by ic_engr on Jan 10th, 2007, 9:34am Hello All, What is the easiest way to simulate the ft of a process in HSPICE. Any enlightment. Tx ic_engr |
Title: Re: Simulate to estimate process ft Post by Croaker on Jan 12th, 2007, 8:55am Bias up the transistor and do an operating point analysis. Then calculate ft = gm/( 2 * pi * (Cgs + Cgd) ) Also, you could run an AC analysis and see where id/ig = 1. |
Title: Re: Simulate to estimate process ft Post by mg777 on Jan 14th, 2007, 8:59pm Note that fT uses an ideal current source excitation, so there is no time constant due to base/gate series resistance (unlike a voltage source excitation). Now the DC input resistance of a MOS transistor is obviously in the GOhm or TOhm range so you may ask why gate resistance is relevant. It's because there is a component of gate (poly) resistance that charges the extrinsic gate-drain capacitance. fT is a good metric for classes of digital circuits that are entirely gm driven - a regenerative flip-flop is a good example. So, a frequency divider is an excellent circuit to leverage fT. But if you're designing an LNA you must look at fmax, or some other bizarre metric that also involves the noise circles. It's very well to play safe and say look at both fT and fmax, but if you know what you're designing you can push your process. M.G.Rajan www.eecalc.com |
Title: Re: Simulate to estimate process ft Post by sivacharan on Jan 21st, 2007, 11:19pm Basic doubt on fT. fT is said to be process constant. But in the expression for fT, it is dependent on gm and cgs. Will the fT vary by varying gm for the same process?? Thanks. |
Title: Re: Simulate to estimate process ft Post by ACWWong on Jan 22nd, 2007, 2:37am fT does vary depending on bias. fT quoted by foundries for a particular process are usually obtained given specific device size, current density, device temperature & supply/bias volatges (best choosen to give a nice high value). It is often the case that the designer will not bias devices for maximum fT, but for other performace paramters. cheers aw |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |