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Design >> Mixed-Signal Design >> Verilog-A model for comparator
https://designers-guide.org/forum/YaBB.pl?num=1168530176

Message started by cat18521 on Jan 11^th, 2007, 7:42am

Title: Verilog-A model for comparator
Post by cat18521 on Jan 11^th, 2007, 7:42am

I am a student in the university and now I'm designing the comparator part of a SAR-ADC.The comparator consists of 3 stages preamplifiers and a regenerative latch.I want to use verilog-a to do it.But I am confused about a thing that whether I should write the verilog-a models for the 3 preamplifiers and the latch and then combine them together or only write a model for the comparator?

If anyone have the verilog-a model for the preamplifier and the latch, can you please send it to me, cause I'm a new bird about the verilog-a.
Thanks a lot!!

my email: ronaldomiao@yahoo.com.cn

Title: Re: Verilog-A model for comparator
Post by Ken Kundert on Jan 11^th, 2007, 8:34am

In general you should write a combined model unless there is some compelling reason for writing separate models and combining them. You do this because it is generally easier to write one model rather than several, and the single model generally runs considerably faster.

Also, it is best if people post any models they might have to this website rather than sending it directly to you so everyone can benefit.

A comparator model is given on the Verilog-AMS page: http://www.designers-guide.org/VerilogAMS/.

-Ken

Title: Re: Verilog-A model for comparator
Post by cat18521 on Jan 11^th, 2007, 2:24pm

to Ken:thank you for your reply!

I have downloaded the comparator model from the webpage you gave.But I find that it is rather too simple.
and many parameters are not included in that model.The comparator I need should have differential input(ip,in)
,differential output(outp,outn),reset signal and clock signal. I have write some code for my preamplifier and latch,
but I am not sure about its correctness.Also, I don't know how to add clock signal into the model and how to define the active time for each stage of the preamplifiers.

If you know ,please give me some advice! Thanks

My preamplifier code:

// VerilogA for addaLabs, cmp, veriloga

`include "constants.vams"
`include "disciplines.vams"

module cmp (ip, in, outp, outn, reset);

inout ip, in, outp, outn, reset;

electrical ip, in, outp, outn, reset;

parameter vo = 0; // output offset voltage
parameter tr = 1n; // rise time
parameter tf = 1n; // fall time
parameter Vt = 0; // threshold voltage
parameter Vdd = 3; // supply voltage
parameter td = 1n; // threshold voltage
parameter cm_voltage = 0;
parameter gain = 10;

real voutp, voutn;

analog
begin

if (V(reset) > 0.5)
voutp = cm_voltage;
else if ( (V(ip) - cm_voltage) > Vt )
voutp = (V(ip) - V(in)) * gain;

else
voutp = (V(ip) - V(in)) * gain;

if (V(reset) > 0.5)
voutn = cm_voltage;
else if ( (V(in) - cm_voltage) > Vt )
voutn = (V(in) - V(ip)) * gain;
else
voutn = (V(in) - V(ip)) * gain;

V(outp) <+ transition (voutp, td, tr, tf);
V(outn) <+ transition (voutn, td, tr, tf);
end
endmodule

My latch code:

// VerilogA for addaLabs, ADClatch, veriloga

`include "constants.vams"
`include "disciplines.vams"

module ADClatch (in, out, reset);

inout in, reset, out;

electrical in, reset, out;

parameter gain = 1000000; // 1EXP+06
parameter rt = 1n ; // risetime, default = 1 ns
parameter td = 1n;
parameter cm_voltage = 0;
parameter vdd = 3;
parameter vss = -3;
real vout;

analog
begin

if (V(reset) > 0.5)
vout = cm_voltage;
else if (V(in) * gain > vdd)
vout = vdd;
else if (V(in) * gain < vss)
vout = vss;
else
vout = V(in) * gain; // V(in) could be positive or negative

V(out) <+ transition (vout, td, rt, rt);

end
endmodule