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Design >> Mixed-Signal Design >> Resistor mismatch in 10bit DAC
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Message started by Vabzter on Jan 15^th, 2007, 12:17am

Title: Resistor mismatch in 10bit DAC
Post by Vabzter on Jan 15^th, 2007, 12:17am

Hello everyone,
I am designing a 10bit DAC in 90nm technology. The topology is Inverted Resistive ladder DAC and I am refering the IEEE paper "A Low Power Inverted Ladder D/A Converter" by Yevgeny Perelman and Ran Ginosar" for the design.I have the following general design questions:
1. How to find out the effects of resistor mismatch in DAC. Which simulations do I perform?
2. Is there and way to find an optimum value of resistances so that the mismatch will be less.
3. Can the mismatch be controlled in the layout only? Or is there and steps I need to so in the design of ladde DAC.
I am new to design so any help would be appreciated..
Thanks a lot in advance,
BR,
Vabzter

Title: Re: Resistor mismatch in 10bit DAC
Post by Visjnoe on Jan 15^th, 2007, 8:54am

Hi Vabtzer,

I have not read the paper yet, but I would proceed in the following manner:

1. Try to find/come up with equations to relate the INL/DNL performance of your DAC to the resistor matching.
Based on those, write a MATLAB Monte-Carlo script that gives you yield in function of resistor matching.
Based on the required resistor matching, determine the size of your resistors. I guess there will not be an optimum for the resistor sizes, just a lower bound (i.f.o DAC yield)

2. Verify the equations and assumptions you made in step(1) using Monte-Carlo simulation in your preferred simulator. If simulations are too time-consuming to run completely at the transistor level, replace all non-critical parts by an AHDL model.

3. As a general remark when designing >10b ADC/DAC: make sure you control the simulator well: you don't want to mix up numerical noise with real noise.

When it comes to resistor matching, improving the size will improve the matching. As far as layout is concerned:
same orientation and proximity should work fine.

Kind Regards

Peter

Title: Re: Resistor mismatch in 10bit DAC
Post by Vabzter on Jan 15^th, 2007, 11:00pm

Visjnoe wrote on Jan 15^th, 2007, 8:54am:

Hi Peter,
Thank you for your help..
BR
Vabzter

Title: Re: Resistor mismatch in 10bit DAC
Post by loose-electron on Jan 30^th, 2007, 2:01pm

Also, do you want to use a ladder DAC? There are arcitectures that are less process dependent.

PWM, or sigma delta if the frequency is low enough. Post some more specifics on what you are trying to do would be good.

Title: Re: Resistor mismatch in 10bit DAC
Post by mists on Jan 30^th, 2007, 9:07pm

another question, what is advantage of this type dac comparable to R2R type.

Title: Re: Resistor mismatch in 10bit DAC
Post by Vabzter on Jan 30^th, 2007, 10:34pm

loose-electron wrote on Jan 30^th, 2007, 2:01pm:

Hi
I am designing a 10bit DAC with inverted ladder topology. The specs are Vout=1.7V, 90nm tech, DNL= 1lsb, INL = 5lsb, conversion rate = 10us . The IEEE paper is uploaded below. I have 2 LSB resistor ladder and 1 MSB ladder which runs in between the 2 LSB ladders. For a perticular input bit the corresponding resistor is shorted out by a switch.E.G 0000000001=>no.0th MSB switch ON and two no.1st LSB switches ON..

The value of LSB resistor is 117ohms and MSB is 3.75Kohms. I want to find the sizes so that the mismatch will be minimum. The intended application is used in control the bias voltages of other circuits.

I was trying with Monte Carlo simulations but dont know how to find the correct plots for size vs mismatch.Being new to design I am not very conversant with this tool.

Actully I have designed the DAC and will start with the simulations so changing the method now is not an option for me..I am doing a masters thesis.

So any help in this regard would be useful.
Thanks for your comments
BR
Vabzter

Title: Re: Resistor mismatch in 10bit DAC
Post by Vabzter on Jan 31^st, 2007, 2:06am

mists wrote on Jan 30^th, 2007, 9:07pm:

another question, what is advantage of this type dac comparable to R2R type.

Hi,
The requirement for me was low power design and low offset voltage. This DAC is monotonic by design. In R-2R the monotonicity depends on opamp at the output. Also this dac is easy to design and has a lower output resistance and parasitic capasitance.
But I am stuck at how to size the resistances so that the mismatch will be minimum.
Thanks
BR
Vabzter

Title: Re: Resistor mismatch in 10bit DAC
Post by loose-electron on Feb 1^st, 2007, 2:55pm

You might want to research your architecture decision a bit first.

Some items to keep in mind --

Resistance values will shift +/-20% from nominal value (process variance common to all elements on the chip)
Resistances will mismatch up to 5% on the same chip
Both of the above are "approximate rules" but good guidelines.

Also don't take the IEEE-JSSC articles as divine truth, there is both good and bad in there. (I can get away with saying that, I am a reviewer for both IEEE JSSC and IEEE MTT)

Ladder DAC's are dependent on current division and the resistor matching associated with it. They are also fussy on layout as well. Give some thought to PWM, Sigma Delta, which is much less dependent on analog characteristics of the process. PWM and SIgma Delta are dependent more on digital duty cycle adjustments than analog accuracy. There are other architectures as well.

- Oh, and the paper did not post, so not sure what you are using there. If this is just academic analysys, then stay with what you have, but if you are going to fabricate this in a piece of silicon, then you may have problems.

good luck with it!!!

Jerry

Title: Re: Resistor mismatch in 10bit DAC
Post by RobG on Feb 7^th, 2007, 2:44pm

OK, I just saw this. For those who couldn't upload the paper, the topology appears to be similar to the old trick of putting a fine-bit resistor string that can be placed across two outputs of a coarse string to get the finer resolution. There appears to be some circuitry to offset the loading, but I didn't look at it closely.

First, I'd be wary of trying to cancel the loading... it may introduce more errors than the mismatch. I'd also be wary of the scheme in general... if it is between two resistor strings it may not be guaranteed monotonic... that said, it may also be a great idea... it's hard to say without diving into the circuit.

Matlab Monte Carlo is best for simulating INL of these types of DACs - spice usually takes too long because you need to check many codes. It is about impossible to get a closed form solution for INL (or even DNL) because it is the maximum error of all the codes. Bastos gives a brief discussion of the issue in his Dec 1998 JSSC paper. Steyart also wrote about the subject in a different paper. Read about what INL is in the Johns/Martin book.... that is what you'll want to simulate. Assume a particular yield (say 99%) and figure out how much area is required to achive that yield. Be aware that systematic errors from layout will produce an error on top of the mismatch error. Give yourself plenty of room... 99.9999% yield is a reasonable simulation goal because you aren't including layout errors.

FWIW, Baker's analysis is incorrect in his purple book.... Your dac would need to be a few acres in size to meet his spec. A rough rule of thumb is sigma(INL) = sqrt(2^N)*sigma(LSB), where N is the number of bits and sigma(LSB) is the standard devition of one code.

You will need mismatch data... low sheet (~30 ohm) poly resistors are poor... on the order of 20%-um (meaning the ratio of two poly resistors, each with an area of 1um^2, with have a SD of 20%). High sheet poly is better, and diffusion resistors match very well, but have voltage coefficients. Both high-sheet and diffusion have significant temp cos.... I think some of the newer text books may have information on mismatch.... In a nutshell, the mismatch decreases as the square-root of the area.

Regarding optimium size, a normal D/A wouldn't have an optimal size... bigger would always be better. However, your structure probably has an optimal area allocation between the coarse/fine resistor strings (as well as number bits resolved by each). Lin/Geiger's paper (March 2006, TCAS-I) may help. I published a paper on the subject too Gregoire: 2004 CICC. However, I expect matlab simulations should be quick, and with a little common sense you can figure it out without knowing the calculus. If you figure it out, publish a tcas-ii paper so I don't have to derive the answer next time :-).

I expect your INL will be determined by the coarse dac, so it will require much of the area.

Layout can only make things worse than simulation - poor layout probably won't affect the standard deviation much, but it can introduce large systematic errors... you need to make sure the layout is insensitive to gradients in temperature and process (sheet resistance). Make sure contact, via, and metal resistances don't introduce errors. Other than that, it is just a matter of making the resistors large enough (area wise) to meet your spec.

Vabzter wrote on Jan 15^th, 2007, 12:17am:

Title: Re: Resistor mismatch in 10bit DAC
Post by Vabzter on Feb 7^th, 2007, 11:01pm

Hi all,
I am sorry for not posting the paper but the size is too large..But here is the libk of the original paper

http://www.ee.technion.ac.il/~ran/papers/Inverted%20Ladder%20DAC.pdf

Thanks,
BR
Vabzter

Title: Re: Resistor mismatch in 10bit DAC
Post by Vabzter on Feb 7^th, 2007, 11:03pm

loose-electron wrote on Feb 1^st, 2007, 2:55pm:

Hi Jerry,
Thanks for your comments. Here is the link for the paper. The size is too large for an attachment.

http://www.ee.technion.ac.il/~ran/papers/Inverted%20Ladder%20DAC.pdf

Thanks,
BR
Vabzter