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Design Languages >> Verilog-AMS >> piecewise source realization
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Message started by Pavel on Jan 15^th, 2007, 1:28am

Title: piecewise source realization
Post by Pavel on Jan 15^th, 2007, 1:28am

Hello

I have convergence problem with picewise voltage source.
Here is my code:

Code:

module SUPPLY_SRC (OUT);
output OUT;
voltage OUT;

parameter real t1 = 1m, t2 = 2m, t3 = 5m, t4 = 7m, t5 = 10m;
parameter real v1 = 0.0, v2 = 3.0, v3 = 3.0, v4 = 0.0, v5 = 0.0;
real offset, slope, a0;

analog begin

@(initial_step) begin
offset = 0.0;
slope = 0.0;
a0 = 0.0;
end

@(timer(t1)) begin
slope = (v2-v1)/(t2-t1);
offset = $abstime;
a0 = V(OUT);
$discontinuity(1);
end

@(timer(t2)) begin
slope = (v3-v2)/(t3-t2);
offset = $abstime;
a0 = V(OUT);
$discontinuity(1);
end

@(timer(t3)) begin
slope = (v4-v3)/(t4-t3);
offset = $abstime;
a0 = V(OUT);
$discontinuity(1);
end

@(timer(t4)) begin
slope = (v5-v4)/(t5-t4);
offset = $abstime;
a0 = V(OUT);
$discontinuity(1);
end

V(OUT) <+ a0 + slope*($abstime - offset);

end

endmodule

Simulation reach 1ms, and then convergence error appears:

Error found by spectre at time = 1 ms during transient analysis `amsAnalysis'.
Matrix is singular (detected at `TB.U1:AUT_flow' and `TB.vdd').

Solution at last successful step (at 1 ms), and last Newton iteration (at 1
ms):
I(TB.U1:AUT_flow): 0 A 0 A
V(TB.vdd): 0 V 0 V

Analysis `amsAnalysis' terminated prematurely due to error.
ncsim: *E,RNALER: Simulation terminated due to analog error.

When I change contibution expression
V(OUT) <+ a0 + slope*($abstime - offset);
to be as follows
V(OUT) <+ slope*($abstime - offset);
simulation terminates, but the signal form isn't what I need.

For discontinuity function I used 1 as argument because it's 1st derivative that breakes, not signal itself.
Am I rigtht in my supposition and what could be a reason of such error?

Thank you in advance.

Pavel.

P.S. In error message I changed intentionnally the name of signal from OUT to AUT, otherwise smily appears intstead: :OUT.

Title: Re: piecewise source realization
Post by Geoffrey_Coram on Jan 15^th, 2007, 5:16am

I think you're giving yourself trouble by setting a0 = V(OUT) and then trying to use this value as part of the contribution V(OUT)<+.

Can you compute a0 from the v's?

Title: Re: piecewise source realization
Post by Pavel on Jan 15^th, 2007, 7:32am

Geoffrey,
The reason of error was exactly as you supposed.
I changed for the following

Code:

.
.
@(timer(t1)) begin
slope = (v2-v1)/(t2-t1);
offset = $abstime;
a0 = v1;
$discontinuity(0);
end

@(timer(t2)) begin
slope = (v3-v2)/(t3-t2);
offset = $abstime;
a0 = v2;
$discontinuity(0);
end
.
.
.

and now it works as I want.

Thanks [smiley=dankk2.gif]

Pavel.

Title: Re: piecewise source realization
Post by Ken Kundert on Jan 15^th, 2007, 10:28am

The problem was that whenever one of your timer function fired, you set a0 = V(out), and so in the final contribution statement you effectively ended up being

V(OUT) <+ V(OUT) + slope*($abstime - offset);

Verilog-A treats contributions as equations rather than assignments, so in a mathematical sense you had

V(OUT) = V(OUT) + slope*($abstime - offset)

You can now subtract V(OUT) from both sides to give

0 = slope*($abstime - offset)

Notice that this is nonsensical because it does not contain anything that can be solved for to make it true. Also notice that the output of the source is effectively left unspecified. What you wanted to do was to base the current output voltage on a previous output voltage, but what you did was to base it on the current output voltage at those times when the timer functions fired.

-Ken

Title: Re: piecewise source realization
Post by Pavel on Jan 16^th, 2007, 4:51am

Ok, Ken. I understood my mistake.

Thanks. [smiley=dankk2.gif]

Pavel.