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Modeling >> Behavioral Models >> Defining both current and voltage at output port?
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Message started by Saran on Jan 15^th, 2007, 1:26pm

Title: Defining both current and voltage at output port?
Post by Saran on Jan 15^th, 2007, 1:26pm

I don't know if I am abusing Verilog-A...but, can't we specify both output voltages and currents in a block. For instance, in this oversimplified and incomplete model of a common source amplifier,

snip..
snip..

ampSig = gain * (V(in) - dcoff);
V(out) <+ ampSig + vds;
I(out) <+ some previously computed value.

snip..
snip..

When I run this sim in spectre, my voltage V(out) is what I am expecting to be..However I(out) returns zero. Is there anything horrible I am doing here? I am playing with Verilog-a modeling. This is a simple module with one input and output port (Common source amp).

Thanks,
Saran

Title: Re: Defining both current and voltage at output po
Post by Ken Kundert on Jan 15^th, 2007, 2:48pm

Conceptually what you are trying to do does not make sense. If you specify the output voltage, then the output current will be determined by the load. If you specify the output current, then the output voltage will be determined by the load. You cannot specify both.

-Ken

Title: Re: Defining both current and voltage at output po
Post by Saran on Jan 15^th, 2007, 3:23pm

Oh..I was just trying to write a test module. I had specified the voltage but I also wanted to see the drain current of the output transitor. I guess it was clear abuse of Verilog-a. I know I should have specified an intermediate node for that. Anyways, thanks for the response.

Title: Re: Defining both current and voltage at output po
Post by Geoffrey_Coram on Jan 16^th, 2007, 6:27am

Saran wrote on Jan 15^th, 2007, 3:23pm:

I know I should have specified an intermediate node for that.

I'm not sure that specifying an intermediate node will help. As Ken said, if you specify the voltage, then the load determines the current, and the most you can do is measure it (not set it).