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Modeling >> Behavioral Models >> Behavioural code for Generating a jittered clock
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Message started by pkdas on Jan 17^th, 2007, 3:23am

Title: Behavioural code for Generating a jittered clock
Post by pkdas on Jan 17^th, 2007, 3:23am

Hi please help me on the above.I need to validate a digiutal system which works fine with ideal clock in VHDL across a jittered clock( of mean frequency 10n and and std dev of around 1n.If anybody has a sample code it will be better.
Thanks,
pd