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Other CAD Tools >> Physical Verification, Extraction and Analysis >> simulation after Place&Route
https://designers-guide.org/forum/YaBB.pl?num=1169084963

Message started by qlmei on Jan 17^th, 2007, 5:49pm

Title: simulation after Place&Route
Post by qlmei on Jan 17^th, 2007, 5:49pm

Hi, everyone

After Place&Route, i import verilog netlist to cadence and got symbol and schematic. If i want to simulate with schematic, how to include the .sdf file?

Title: Re: simulation after Place&Route
Post by ywguo on Jan 22^nd, 2007, 6:30am

Hi,

I think the .sdf file is a back-annotation file for gate-level simulation of verilog or VHDL. So you need not import the verilog netlist to a cadence composer. :) In some HDL simulator, the .sdf file is read and the post-layout timing information is annotated at each path and gates, flip-flops, etc.

Yawei

Title: Re: simulation after Place&Route
Post by marjo marasigan on Feb 18^th, 2007, 9:28pm

Hi!

Is there a way for us to import the .sdf file into cadence?

We have already simulated our verilog file together with the .sdf using NCLaunch. But we need to import the verilog file together with the .sdf into cadence in order to perform mixed signal simulation.. Is there any way? Help..

-marjo

Title: Re: simulation after Place&Route
Post by zhong on Feb 26^th, 2007, 12:16am

I guess what you were asking is to import SDF to Cadence Virtuoso DFII database ? And you have imported Verilog gate level netlist into the DFII.

Actually you don't need to "import SDF" to be "DFII database" . SDF file is a standard text, you can directly backannotate SDF text file to your Verilog gate level netlist during ncelab stage either in command mode or GUI mode.

Here is what you need to do ..
For example , you have raw SDF file "my_sdf.txt"

1. run ncsdfc to generat compiled SDF file
ncsdfc my_sdf.txt ---> generat my_sdf.txt.X which is compiled SDF file

2. Prepar SDF command file say MY_SDF_CMD.txt , for example
COMPILED_SDF_FILE = "PATH_TO_YOUR_SDF_FILE/my_sdf.txt.X" ;
SCOPE = top.I0.I1 ;
----- This means that your verilog gate level block is top.I0.I1 in top level design context .

....

3. In AMS-ADE or AMS-HED GUI
In ncelab options -> SDF command field ,
please fill path_to_your_sdf_command_file/MY_SDF_CMD.txt

So that SDF will backannotate to the verilog gate level block ..

Hope this helps ..
Zhong

Title: Re: simulation after Place&Route
Post by marjo marasigan on Feb 26^th, 2007, 1:49am

Thanks for the reply Sir Zhong! :)

Actually, we have already done the backannotation of our verilog file. But we still need to simulate the verilog file (with the corresponding delays from the sdf) together with the schematic and layout of our analog modulator in Virtuoso.. Do you know of any options that we may have to be able to do this?
:)

-marjo

Title: Re: simulation after Place&Route
Post by zhong on Feb 26^th, 2007, 10:26pm

In fact , My previous reply did address how to backannotate SDF to the verilog code in DFII schematic. It should address your question. For example of my SDF cmd file ..
top.I0.I1
top is schematic
top.I0 is shematic
top.I0.I1 is verilog module (gate level netlist) for SDF backannotation to .

This is way I use to backannotate SDF to analog-mixed design in DFII GUI all the time .

Hope this helps ..