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Design >> Analog Design >> Topology of Voltage Buffer
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Message started by avlsi on Jan 23^rd, 2007, 3:04am

Title: Topology of Voltage Buffer
Post by avlsi on Jan 23^rd, 2007, 3:04am

Hi, I must design a voltage buffer driving drain of of transistors.

These PMOS W/L are quite large, so the capacitance itself is around 30 pF. In this case suggest me a toplogy to buffer voltage from a resistive divider.

Any suggestions on design are also welcome.