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Simulators >> Circuit Simulators >> Giving vector inputs in Spectre
https://designers-guide.org/forum/YaBB.pl?num=1169796299

Message started by rgnanadavid on Jan 25^th, 2007, 11:24pm

Title: Giving vector inputs in Spectre
Post by rgnanadavid on Jan 25^th, 2007, 11:24pm

Hi i'm trying to simulate a register file in Spectre. but the problem is i have wide buses for data and address. And every time i'm able to define those inputs only as pulse waveforms, bit by bit.. Is there any way to give these as vector inputs..(Tspice has this option .vector). Also while viewing results can i group the related signals and view them as a bus just like in a Verilog simulator...

Title: Re: Giving vector inputs in Spectre
Post by Andrew Beckett on Jan 26^th, 2007, 6:39am

Yes, this is possible with the ISR10 or later of MMSIM6.0 Version 6.0.1.174 or later of spectre. Syntax is:

For vector file

In Spice netlist:

Code:

.vec 'vector_filename' [HLCheck = 0|1]

In Spectre netlist:

Code:

vec_include 'vector_filename' [HLCheck = 0|1]

vector_filename -- the filename of the digital vector file.

HLCheck = 0 | 1 Special flag (default=0) which turns on checking for the H and L states for input signals. HLCheck is a special flag ( default = off) to create the vector output check for the H and L states of input signals. Bidirectional and output signals always check H and L states and are unaffected by the HLCheck flag. Normally, users do not need to use the HLCheck flag

For VCD/EVCD file

In Spice netlist:

Code:

.vcd "vcd_filename" "signal_info_filename"
.evcd "evcd_filename" "signal_info_filename"

In Spectre netlist:

Code:

vcd_include "vcd_filename" "signal_info_filename"
evcd_include "evcd_filename" "signal_info_filename"