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Simulators >> AMS Simulators >> errors when compiling modules from ahdlLib
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Message started by Na Kong on Jan 27^th, 2007, 3:03pm

Title: errors when compiling modules from ahdlLib
Post by Na Kong on Jan 27^th, 2007, 3:03pm

It says:
======================================================================
Compiling
/software/Cadence/IC5141/tools/dfII/samples/artist/ahdlLib/ind/veriloga/veriloga.va in cellview ahdlLib.ind:veriloga
ncvlog: 05.81-p002: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncvlog: *E,DLWRIT: Intermediate file for module ahdlLib.ind:veriloga (VST) could not be opened for writing (System error).
Verilog-AMS compile failed for cellview ahdlLib.ind:veriloga
======================================================================

Does it mean the modules should be writable first, then can be compiled? But that isn't reasonable. Could anybody tell me how to deal with this? Thanks a lot!

Na

Title: Re: errors when compiling modules from ahdlLib
Post by Andrew Beckett on Jan 28^th, 2007, 2:13pm

There are two solutions - one is to run "amsLibCompile" in <instdir>/tools/dfII/bin. This will compile all the Verilog-A libraries in the DFII installation. This is a configuration step during installation, but you can run it afterwards. To do this though, you'd need write access to the library.

The other approach is to add:

ASSIGN ahdlLib TMP ./ahdlLib_tmp

into your cds.lib file. This tells it to use ahdlLib_tmp in the working dir as a writable temporary directory for derived data from the ahdlLib - and so ncvlog will be able to compile into that.

Regards,

Andrew.

Title: Re: errors when compiling modules from ahdlLib
Post by Na Kong on Jan 28^th, 2007, 6:03pm

Many thanks!

Na