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Design >> Analog Design >> LDO design
https://designers-guide.org/forum/YaBB.pl?num=1170049479

Message started by rf_jay on Jan 28^th, 2007, 9:44pm

Title: LDO design
Post by rf_jay on Jan 28^th, 2007, 9:44pm

Can we design a stable LDO from 7volt input to 3.3volt output in microwatt range. can we use the onchip cap for this application? if yes how big cap?

thanks in advance,
jay.

Title: Re: LDO design
Post by loose-electron on Jan 30^th, 2007, 1:45pm

Jay:

The answer is yes....

but thats not a very useful answer is it?
Got any specifics on such a design that you need to cover?

The question is pretty global, so you are not going to get a lot of useful answers IMHO.

Title: Re: LDO design
Post by rf_jay on Feb 2^nd, 2007, 3:40am

Thanks for the reply.

The chip has around 10k digital logic. the supply for those is from the output of this LDO. The chip has limitation on number of pins and hence using external cap.

can you please furnish me some docs/pdfs of examples where in capacitor less LDO's are tested on chip.

Having these docs will be great.

regrds.
jay.

Title: Re: LDO design
Post by ywguo on Feb 7^th, 2007, 1:17am

Hi, jay,

I designed a LDO w/o external cap for a small digital circuit and an EEPROM. The simulation proved large transient ripples when the loading (digital circuit) were operating.

I think the first problem is to model the transient current supply of a 10K gates digital circuit.

The second problem is a circuit topology. The conventional topology often needs very huge external cap.

Best regards,
Yawei