The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> inductance estimation with ASITIC https://designers-guide.org/forum/YaBB.pl?num=1170064839 Message started by arunm on Jan 29th, 2007, 2:00am |
Title: inductance estimation with ASITIC Post by arunm on Jan 29th, 2007, 2:00am Hi, I am using a symmetric square inductor for my VCO. I tried estimating its parasitics using ASITIC. When I compared the parasitic cap from the pi model of asitic to the cap that cadence extracted (I extracted the cap as lumped at the two ends), I found that the ASITIC cap value was way too low. I think the technology file that I give as input to ASITIC is accurate. Is ASITIC reliable for estimating the parasitic cap? Thanks, Arun |
Title: Re: inductance estimation with ASITIC Post by ACWWong on Jan 29th, 2007, 3:22am My experience with ASITIC is quite good, and have used the models generated on chips that have performed close to expected. Are you sure you are using the pix or pi2 solver and coded your techfile correctly ? The only issue with ASITIC I have found is that it sometimes doesn;t converge on a sensible answer (ie. series R with parasistic Csub in NaN or something). When it does converge on a resonable answer I have found it matches well with ADS Momentum (when you rationalise the Momentum pi model) as well as real measurements. When you say cadence extracted. do you mean Assura/Diva RCX or FastHenry ? Remember the parasitic Csub values extracted in the pix/pi2 solver of ASITIC are inteneded to be used in conjunction with the series L, series R, and Rsub1, & Rsub2 values to give inductor performance. As such it might not necessarily be the case that Csub1+Csub2 be equal to a Metal-oxide-groundplane capacitor calculation. ASITIC does have a pure cap solver, you might try looking at that if you are only interested in parasitic C (as would be extraed in AssuraRCX/divaLPE). cheers aw |
Title: Re: inductance estimation with ASITIC Post by arunm on Jan 29th, 2007, 6:25am Thanks Mr. Wong. I was using the PIX command in ASITIC. And by cadence extraction, I meant Assura RCX. Will the simple model of ASITIC be accurate enough to be used in simulations? Currently, to simulate the distributed nature of the inductor, I am doing the following. I get the inductance and series resistance values from FastHenry (ASITIC inductance and series resistance were also nearly the same). I get the parasitic cap from Assura RCX. Then I split the inductance, series resistance and cap equally to make five segments and use this for simulation. Is this a reasonable thing to do? I am using UMC 0.18um CMOS RF process with the thick top metal option. What is a reasonable value for Q(max) that can be expected if we don't use any patterned shields? Thanks, Arun |
Title: Re: inductance estimation with ASITIC Post by ACWWong on Jan 29th, 2007, 6:57am The parasitic C should not be ideal. Assura -RCX will only give you an ideal area/fringing capacitance to substrate with no associated loss (Rsub). In doing so, your parasitic C will not degrade Q when in actual fact it will. So I would not recommend the method you propose. In ASITIC, if you have an accurate techfile (including importantly substrate resistivity!!), then you should also be including the substrate contact (using halo), so you can extract accurately the Rsub value, and hence better model the indcutor. Have you also insured you have setup the chip size and fft size correctly ? Anyway ASITIC differs from most inductor pi models used by foundries/other tools in that the parasitics are rationallised into a single R C structure: Node1 -- ind -- Rs -- Node2 | | Csub1 Csub2 | | Rsub1 Rsub2 | | sub sub compared to the more usual (ignoring the small parallel C across Node1 & node2) Node1 -- ind -- Rs -- Node2 | | Cox1 Cox2 | -------| |-----------| Rsub1 Csub1 Csub2 Rsub2 | | | | sub sub sub sub but is fairly straight forward to map the convention parasitic C model with those generated in ASITIC. I used UMC 0.18um CMOS RF process a few years ago and I recall they have inductors modelled in their kit and documentation.... so you should try your modelling technique on a known kit structure. Max Q depends on your inductor value & design... and is not much use to you if not at the frequency you want. I reiterate, I have had designed production silicon using inductors modelled in ASITIC. cheers aw |
Title: Re: inductance estimation with ASITIC Post by arunm on Jan 29th, 2007, 8:09am Thanks a lot for the detailed reply Mr.Wong. I am using a symmetric square spiral. If the spacing between turns is small, then I see that the capacitance between the two inductors is quite large (infact, it tends to dominate the cap to substrate). How will this be captured in the pi model of ASITIC? Thanks, Arun |
Title: Re: inductance estimation with ASITIC Post by ACWWong on Jan 29th, 2007, 11:38am it should be included in the ASITIC simulation, and so you will see the impact by running a couple of simple examples of differing turns spacing. If you have detailed queries with regards the algorithms used you should try the ASITIC website FAQ page. http://rfic.eecs.berkeley.edu/~niknejad/doc-05-26-02/faq.html where you can links to the underlying methodology. You might try other tools to extract the symmetrical inductor (Sonnet, Momentum etc.) if you are not happy/do not trust ASITIC's output. Also you can do a couple of simple sanity check hand calculations, for this I recommend some basic texts like Thomas Lee's "The Design of CMOS Radio-Frequency Inegrated Circuits" or a quick google paper search. cheers aw |
Title: Re: inductance estimation with ASITIC Post by Prabhu on Mar 14th, 2007, 11:22am ASITIC may be useful in modeling single ended inductors only where the capacitance of the metal to the substrate is the major parasitic capacitance. In differential inductors as Arun said the mutual capacitance between conductors will be dominating which is not accurately captured ( if captured at all ! ) in ASITIC. I simulated differential inductors with various spacing (from 1um to 5um ) and approximately equal surface area. The capacitances ( Cs1, Cs2 ) given by ASITIC are almost the same in all the cases. Prabhu |
Title: Re: inductance estimation with ASITIC Post by ACWWong on Mar 15th, 2007, 7:50am Hi Prabhu, Yes it doesn't really surprise me that Cs1 or Cs2 didn't increase as the spacing was reduced. This is because the pi network is NOT a physical model but a lumped represenatation of the spiral of the 2-port parameters computed at a particular frequency. The impact of reducing the spacing is likely to be reflected in ASITIC for your differential inductors in the way that the self inductance increases rapidly as the simulation frequency approaches a lowered SRF, that is that the interwinding capacitance is captured in the values and changes in L at higher frequencies rather than in the values of Cs1 and Cs2 (which reflect substrate losses). Also even in differential symetrical spiral, i don't think the interwinding is dominant over the substate capacitance, because each segments capacitance does still sum as series capacitances between the two ports (although it is larger than in a single ended spiral), but it all depends on your technology and inductor size. Do a google or IEEE search for papers by John R. Long on the topic. Anyway, in summary I would still recommend ASITIC above just using Assura-RCX in trying to build up a spiral inductor model, be it single of differential. It would interesting if you redid your modeling in a 3D simulator (Sonnet etc.) for your differential spirals to see the difference in the model performance between ASITIC and a full EM solver. Cheers aw |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |