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Simulators >> AMS Simulators >> Spectre subcircuits in AMS Designer
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Message started by Pavel on Jan 30^th, 2007, 6:37am

Title: Spectre subcircuits in AMS Designer
Post by Pavel on Jan 30^th, 2007, 6:37am

Hello

Is Hierarchy Editor / SimVision are capable to "view" insite of Spectre netlist in form of subcircuit.

Regards.

Pavel.

Title: Re: Spectre subcircuits in AMS Designer
Post by jbdavid on Feb 1^st, 2007, 1:44am

Last I checked, Only Verilog(ams) netlists could be "seem" by the simulator.. Modelfiles and other spectre subcircuits would not be visible that way..
but If its REally a subcircuit, all you need to do is translate the spectre to structural Verilog(ams)
If its large, a perl script might help.. in fact Cadence folks might be able to provide you with one that they have..

Title: Re: Spectre subcircuits in AMS Designer
Post by Pavel on Feb 1^st, 2007, 2:41am

Thank you for answer

Quote:

but If its REally a subcircuit, all you need to do is translate the spectre to structural Verilog(ams)

I did it already, but the AMS behaviour is different from one of Spectre.

Spectre behaviour was tested under Analog environment. It's reference for the moment.
Now we need the same block in AMS Designer. I converted block in AMS and simulated it in AMS Designer.
Its behaviour was different "Reference Spectre subcircuit", simulated in Analog Environment.

This morning I tried to instantiate "Reference Spectre subcircuit" in AMS Designer.
Its behaviour was also different from one, simulated in Analog Environment behaviour.

Pity, that I can't see inside of the Spectre block in order to troubleshoot behaviour mismatch.

Regards.

Pavel.

Title: Re: Spectre subcircuits in AMS Designer
Post by Pavel on Feb 1^st, 2007, 3:17am

When I use "Spectre subcircuit" block in AMS designer, Hierarchy Editor shows symbol in View Found column, but not spectre.
So, how can I be sure that elaborator takes spectre netlist in consideration.

Regards.

Pavel.

P.S. I created Spectre-netlisted cell according to AMS manual.

Title: Re: Spectre subcircuits in AMS Designer
Post by zhong on Feb 3^rd, 2007, 11:28am

Pavel,
There are two ways to take the spectre/spice netlist as sub blocks into AMS designer for mixed-signal verification.
1st method
. In HED , you can directly switch to the block from anyother view to "sourcefile"
It's easy in HED -> select one cell -> set cell view -> sourcefile
In source file browser form , you choose spectre/spice netlist.
After this done , the block bind to the spectre/spice source file

Note. if you have level up schematic/verilogams/verilog instantiate this spectre/spice netlist which has the bus connectiion says

cellA I0 (.A(X)) ; // X and A say 4 bits bus
In fact the spectre/spice netlist does not have bus , they are all scalar for example
subckt cellA A_0 A_1 A_2 A_3

Then, you need to define sourcefile_opt in HED
HED -> view -> properties(on)
You will see the sourcefile_opt colum in HED
type-in
-auto_bus -bus_delim _

So that AMS will merge A_0 -> A_3 to be A[0:3] and match the level up bus connectivities .
This is compresive solution for bringing spice/spectre block as sub block for the AMS verification.

2nd method.
If you don't have bus/scalar situation
You can also simply switch cellA to syymbol and add the spetre/spice netlist into you modelfile .

BTW, to probe the simulation result in spice netlist. you can't use tcl from simvision. You need to save the signal within spice block via analog control file. It can be done in AMS-in- ADE GUI which generated control file automatically or standalone analogcontrol file provided by user and load it in AMS-in-HED GUI

Hope this helps .

Title: Re: Spectre subcircuits in AMS Designer
Post by Andrew Beckett on Feb 7^th, 2007, 4:20am

I'm also concerned that you're seeing different behaviour between a subcircuit and an equivalent Verilog-AMS representation of the block. You should report this to Cadence customer support so that they (we) can investigate further.

Regards,

Andrew.