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Measurements >> Phase Noise and Jitter Measurements >> Divider retiming strategy
https://designers-guide.org/forum/YaBB.pl?num=1170258100

Message started by Visjnoe on Jan 31^st, 2007, 7:41am

Title: Divider retiming strategy
Post by Visjnoe on Jan 31^st, 2007, 7:41am

Dear all,

consider an asynchronous div-by-N divider which is retimed by a FF. Assume the input of the divider is clocked at the positive edge of the incoming (clock) signal.

At which edge should the retiming FF be clocked? I would guess that the negative egde is the better choice
(robustness).

Further on: are there better retiming strategies or is the single FF most common?

Kind Regards

Peter

Title: Re: Divider retiming strategy
Post by mg777 on Feb 1^st, 2007, 9:08pm

Is there clock recovery involved?

A robust sampling strategy would be to do an early-late comparison with a DLL. This may be economical only for specialized blocks, not for cells. It's interesting how analog and digital folks treat timing closure very differently.

M.G.Rajan
www.eecalc.com

Title: Re: Divider retiming strategy
Post by Visjnoe on Feb 1^st, 2007, 11:54pm

Dear mg777,

there is no clock recovery involved: it's just retiming of a divided CLK to minimize the jitter through accumulation by an asynchronous divider.

If the divider is triggered by pos edge of the input, I would think it is not save to trigger the retiming FF at the output by the same pos edge of the input, for reasons of FF set-up/hold time basically.

Kind Regards

Peter