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Design >> Mixed-Signal Design >> About feedback DAC reference voltage in SDM
https://designers-guide.org/forum/YaBB.pl?num=1170394389

Message started by camellok on Feb 1^st, 2007, 9:33pm

Title: About feedback DAC reference voltage in SDM
Post by camellok on Feb 1^st, 2007, 9:33pm

Dear All,
I have designed and simulated a MASH 2-1-1 sigma-delta modulator in MATLAB, SWITCAP and Cadence for simulations. Since the supply voltage is 1.8V, I use the reference voltage of 1V in each (+ve/-ve) branch for simulation. In MATLAB/SWITCAP simulation, the maximum input signal amplitude is 1.3Vpp with 2Vpp reference voltage and so the overload level is about -3.5dB. It gives about DR of 80dB in these simulations. But, when I worked in pre-simulation in Cadence, using the same reference, the maximum input signal amplitude can only be about 0.6Vpp and thus the DR is severely limited by 64dB. However, the peak SNDR recovered to about 79dB if the reference votlage increased to 3Vpp but the maximum input signal amplitude is still limited about 1.2Vpp. So, the overload level seems to be much reduced, which made me troublesome why this is so? :(Could anyone tell me?

Best regards,
Camel

Title: Re: About feedback DAC reference voltage in SDM
Post by panditabupesh on Feb 11^th, 2007, 2:46pm

Hello
As a first thing I would suggest is to separate the supplies for switches, or replace them with ideal switches, in your cadence simulations.

Bupesh