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Design Languages >> Verilog-AMS >> Upsampler
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Message started by shirin_br on Feb 2^nd, 2007, 2:41am

Title: Upsampler
Post by shirin_br on Feb 2^nd, 2007, 2:41am

Hello All,

I need to make the behavioral model for Upsampler with factor of L in verilog-AMS. But so far any function that I made did not work. I would appreciate anyone who has done the same, or maybe if has some suggestions, give some hints to me.

Thank you very much.

Title: Re: Upsampler
Post by Geoffrey_Coram on Feb 2^nd, 2007, 5:07am

Did you try using the timer event?

Title: Re: Upsampler
Post by shirin_br on Feb 2^nd, 2007, 6:09am

Yes, I did. But the problem is I should do it by adding zeros in between, two samples. So, there should be a function which gets the samples in the input, the sampling frequency and upsampling fatcor(L) as parameters.

Then it should work as this: divide the period time(T) by the factor, keep the sampled signal for T/L time, add L-1 zeros in each time interval of T/L and repeat this with the frequency of 1/T.

The problem with timer is that I can not use any analog operation inside it.

Title: Re: Upsampler
Post by Geoffrey_Coram on Feb 5^th, 2007, 5:28am

shirin_br wrote on Feb 2^nd, 2007, 6:09am:

The problem with timer is that I can not use any analog operation inside it.

You can't do a contrib, but you should be able to do a sample.

Code:

module upsamp(in, out);
inout in, out;
electrical in, out;
parameter real T = 1u from (0:inf);
parameter integer L = 4 from [1:inf];
real vout;
integer count;

analog begin
@(initial_step or timer(0, T/L)) begin
if (count % L == 0)
vout = V(in);
else
vout = 0;
count = count + 1;
end

V(out) <+ transition(vout, 0, T/(L*10.0));
end
endmodule

I'm not sure if you want the transition there or not, or what the rise time should be. The timer should fire at the upsampling period (T/L) but only sample the input every Lth time, otherwise setting vout to zero.

Title: Re: Upsampler
Post by shirin_br on Feb 5^th, 2007, 6:44am

Hi,

Thank you so much for the help. I had made also something which was working as upsampler, but it was in 2 different blocks, so it was not the optimum solution. The main block was a simple sample and hold but it had a clock input with T/L duty cycle.

Thank you again,
/Shirin