The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> How to send a string in a verilog-ams block
https://designers-guide.org/forum/YaBB.pl?num=1170418039

Message started by shirin_br on Feb 2^nd, 2007, 4:07am

Title: How to send a string in a verilog-ams block
Post by shirin_br on Feb 2^nd, 2007, 4:07am

Hi,

I'm making a block to work as a probe. So I want to send a file as input of the block and plot it. Some how I should manage to send the filename to the probe and ask for the output.
Does anyone know how to send a strng into a block? I could not find any thing in the book yet.

Thank you.

Title: Re: How to send a string in a verilog-ams block
Post by Geoffrey_Coram on Feb 2^nd, 2007, 5:06am

Verilog doesn't support strings; SystemVerilog does.

String literals in Verilog can be handled as arrays of "reg" variables, where each character is an 8-bit value. A little hard to use this, though, to open files.

Title: Re: How to send a string in a verilog-ams block
Post by jbdavid on Feb 9^th, 2007, 3:08am

I guess its NOT the same thing..
but I recently used the new Verilog-A string parameter on a block, which I set to a Design Variable so that I could change the filename from and Ocean script..

it works nicely..
..
..
parameter string myFileName = "Module_Output_file%D_%T.dat";
..
..
analog begin
@initial_step("tran") begin
FileHandle = $fopen( myFileName);
end

---
In verilog-D you can use a register to hold a string value, (8 bits/character)
and until the latest version supports string parameters, you can just leave the TYPE undefined
parameter myFileHandle = "myDefaultFileName.dat"
initial begin
filehandle = $fopen(myFileHandle);
But in digital side , at least in cadence the %T type code isn't supported in the $fopen.